82551IT — Networking Silicon
Note: The 82551IT detects a system error for any parity error during an address phase, whether or not it is
involved in the current transaction.
5.2.1.2
Bus Master Operation
As a PCI Bus Master, the 82551IT initiates memory cycles to fetch data for transmission or deposit
received data and to access the memory resident control structures. The 82551IT performs zero
wait state burst read and write cycles to the host main memory. Figure 7 and Figure 8 show
memory read and write burst cycles. For bus master cycles, the 82551IT is the initiator and the host
main memory (or the PCI host bridge, depending on the configuration of the system) is the target.
Figure 7. Memory Read Burst Cycle
CLK
1
2
3
4
5
6
7
8
9
10
FRAME#
AD
ADDR
DATA
DATA
DATA
DATA
DATA
MR
BE#
BE#
C/BE#
IRDY#
TRDY#
DEVSEL#
Figure 8. Memory Write Burst Cycle
CLK
1
2
3
4
5
6
7
8
9
10
FRAME#
ADDR
DATA
DATA
DATA
DATA
DATA
AD
MW
BE#
BE#
C/BE#
IRDY#
TRDY#
DEVSEL#
The CPU provides the 82551IT with action commands and pointers to the data buffers that reside
in host main memory. The 82551IT independently manages these structures and initiates burst
memory cycles to transfer data to and from them. The 82551IT uses the Memory Read Multiple
(MR Multiple) command for burst accesses to data buffers and the Memory Read Line (MR Line)
22
Datasheet
INTEL [ INTEL ]
