Signal Description
a delayed read or delayed write transaction, the Intel® 6702PXH 64-bit PCI Hub will allow
memory reads, split completions and writes to pass the transaction. A retry is not considered an
error condition and so there is no error logging or reporting done on a retry.
2.12.5.2.10 Split Response
The Intel® 6702PXH 64-bit PCI Hub can receive split response for memory reads, I/O and
configuration read and write transactions.
2.12.5.2.11 Target Termination Initiated by the Intel® 6702PXH 64-bit PCI Hub
The Intel® 6702PXH 64-bit PCI Hub returns a target retry to an initiator when any of the following
conditions is met:
• A new memory read transaction and the Intel® 6702PXH 64-bit PCI Hub delayed transaction
queue is full.
• A memory read or write to CSR space and a previously posted write to CSR space has not yet
internally completed.
• A LOCK transaction has been established from PCI Express to PCI.
• A memory write transaction and the Intel® 6702PXH 64-bit PCI Hub has no free buffer space
to accept the write.
• A memory write is from a master other than the master that was previously retried (starvation
prevention mechanism).
• A configuration transaction to the secondary configuration space and a previously posted
memory write to CSR space has not yet internally completed.
• The Configuration Lockout bit is set in the PXH_CONFIG register and the Intel® 6702PXH
64-bit PCI Hub is being configured locally after a cold boot sequence or during normal system
operation.
The Intel® 6702PXH 64-bit PCI Hub never retries a completion since it always has enough buffer
space for all split requests it sends out. No transaction information is retained on any writes.
The Intel® 6702PXH 64-bit PCI Hub disconnects an initiator when one of the following conditions
is met:
• The Intel® 6702PXH 64-bit PCI Hub cannot accept any more write data and an ADB is
reached.
• A split completion packet is being sent, an ADB is reached, and the Intel® 6702PXH 64-bit
PCI Hub read buffers are running dry.
• A CSR memory read or write occurs after the first data phase.
• The inversed decode window ends and an inbound write is in progress, regardless of write
buffer availability.
The Intel® 6702PXH 64-bit PCI Hub returns a target abort to PCI when:
• A split completion packet is sent to a PCI-X agent and the split cycle target aborted on the
PCI Express bus (or peer PCI bus for Intel® 6702PXH 64-bit PCI Hub).
• A configuration read or write occurs with address or data parity errors or attribute phase parity
errors.
Intel® 6702PXH 64-bit PCI Hub Datasheet
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INTEL [ INTEL ]
