Signal Description
2.12.6.4
Split Transactions
2.12.6.4.12 Completer Attributes
Table 2-21. Intel® 6702PXH 64-bit PCI Hub Implementation Completion Attribute Fields
Attribute
Function
Byte Count Modified (BCM)
The Intel® 6702PXH 64-bit PCI Hub sets this bit only in NT mode
when the burst read starts from within 3 data phases of the BAR
boundary and crosses the BAR boundary.
Split Completion Error (SCE)
The Intel® 6702PXH 64-bit PCI Hub will only set this bit if a memory
read command from PCI-X master or target aborted on the PCI
Express* bus, and also for byte count out-of-range error in NT mode.
Split Completion Message (SCM)
This bit shadows the SCE bit.
2.12.6.4.13 Requirements for Accepting Split Completions
The Intel® 6702PXH 64-bit PCI Hub asserts PADEVSEL# and discards the data if the Requester
ID matches the bridge, but the tag does not match that of any outstanding requests from this device.
2.12.6.4.14 Split Completion Messages
The Intel® 6702PXH 64-bit PCI Hub can only generate error messages for cycles that cross the
bridge and which master or target abort. No DWord cycles that require completion (i.e. I/O cycles)
will cross the bridge. Therefore, the Intel® 6702PXH 64-bit PCI Hub can only generate a “PCI-X
Bridge Error” completion message for the memory read commands as indicated in Table 2-22.
Table 2-22. Split Completion Abort Registers
Index
Message
00h
Master-Abort: The Intel® 6702PXH 64-bit PCI Hub encountered a Master-Abort on the
destination bus.
01h
Target-Abort: The Intel® 6702PXH 64-bit PCI Hub encountered a Target-Abort on the
destination bus.
2.12.7
LOCK Cycles
A lock is established when a memory read from the PCI Express bus that targets a PCI bus agent
with the lock bit set is responded to with a PATRDY# by a PCI target. The bus is unlocked when
the Unlock Special Cycle is sent on the PCI Express interface. When the PCI bus is locked, all
inbound memory transactions from that bus are retried. The Intel® 6702PXH 64-bit PCI Hub
inbound read prefetch engine stops issuing any more requests on the PCI Express bus. Note though
that read completions for inbound read requests issued ahead of the lock being established on the
PCI bus could return on the PCI Express bus after the PCI lock has been established, and the Intel®
6702PXH 64-bit PCI Hub accepts them.
Once the bus is locked, any PCI Express cycle to PCI will be driven with the PALOCK# pin
asserted, even if that particular cycle is not locked. This should not occur, because under lock, peer-
to-peer accesses will be internally blocked and the MCH should not be sending any non-locked
transactions downstream.
Intel® 6702PXH 64-bit PCI Hub Datasheet
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