Signal Description
2.12.5.2
PCI-X Mode Transaction Termination
2.12.5.2.6 Initiator Disconnect or Satisfaction of Byte Count
As a PCI-X master, the Intel® 6702PXH 64-bit PCI Hub uses normal termination (initiator
disconnect or satisfaction of byte count) if PADEVSEL# is returned by the target within six clock
cycles after the address phase. The Intel® 6702PXH 64-bit PCI Hub terminates a transaction when
one of the following conditions are met:
• All write data indicated in the byte count of the write transaction is transferred from
Intel® 6702PXH 64-bit PCI Hub data buffers to the target. The Intel® 6702PXH 64-bit PCI
Hub never does an initiator disconnect on a write before the byte count size has been satisfied.
• An initiator disconnect occurs at the next ADB on a split read completion because the
Intel® 6702PXH 64-bit PCI Hub data buffer has run dry.
• An initiator disconnect at the next ADB when the master latency timer has expired and the
Intel® 6702PXH 64-bit PCI Hub’s bus grant signal is de-asserted.
2.12.5.2.7 Master Abort Termination
If a Intel® 6702PXH 64-bit PCI Hub initiated transaction is not responded to with PADEVSEL#
within six clocks after address phase, the Intel® 6702PXH 64-bit PCI Hub terminates the
transaction with a master abort. The Intel® 6702PXH 64-bit PCI Hub sets the received master
abort bit in the secondary status register. Read requests (configuration, I/O, memory) that receive
master abort termination are sent back to PCI Express / peer PCI with a master abort status.
Delayed write requests that receive master abort are sent back to PCI Express with a master abort
status.
Note: When the Intel® 6702PXH 64-bit PCI Hub performs a Type 1 to special cycle translation, a master
abort is the expected termination for the special cycle on the target bus. In this case, the master
abort received bit is not set, and the Type 1 configuration transaction is disconnected after the first
data phase.
2.12.5.2.8 Target Termination Received by the Intel® 6702PXH 64-bit PCI Hub
If the Intel® 6702PXH 64-bit PCI Hub receives a target abort, and the cycle requires completion
on the PCI Express bus, the Intel® 6702PXH 64-bit PCI Hub will return the target abort status to
PCI Express. The Intel® 6702PXH 64-bit PCI Hub sets the received target abort status bit in the
secondary status register for all target aborts it receives on the PCI bus. Target abort can happen on
any data phase of a PCI-X transaction, and a read completion packet to PCI Express / peer PCI,
incurring a target abort in the middle of the packet would return valid data to the point of target
abort and all 1s for the reminder of the length and a target abort completion status for the entire
packet.
2.12.5.2.9 Disconnect and Retry
If the Intel® 6702PXH 64-bit PCI Hub receives a disconnect response (single data phase or at next
ADB) from a target, it will re-initiate the transfer with the remaining length. When the
Intel® 6702PXH 64-bit PCI Hub receives a retry, it will wait at least two PCI clocks before it
retries the transaction. If the retried transaction is a write, the Intel® 6702PXH 64-bit PCI Hub will
retry the write till it completes normally or with a target or master abort. If the retried transaction is
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Intel® 6702PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
