Signal Description
transaction, the Intel® 6702PXH 64-bit PCI Hub will allow memory reads and writes to pass the
transaction. A retry is not considered an error condition, and so there is no error logging or
reporting done on a retry.
2.12.5.1.5 Target Termination Initiated by the Intel® 6702PXH 64-bit PCI Hub
The Intel® 6702PXH 64-bit PCI Hub returns a target retry to an initiator when any of the following
conditions is met:
• A new memory read transaction occurs and the Intel® 6702PXH 64-bit PCI Hub delayed
transaction queue is full.
• A memory read occurs that has already been queued, but has not completed on the
PCI Express bus.
• A memory read occurs that has been queued and completed on the PCI Express bus but
ordering rules require an outbound posted write to complete ahead of it.
• A memory read or write to CSR space occurs and a previously posted write to CSR space has
not yet internally completed.
• A LOCK transaction is established from the PCI Express to the PCI bus.
• A memory write transaction occurs and the Intel® 6702PXH 64-bit PCI Hub has no free
buffer space to accept the write.
• A memory write occurs from a master other than the master that was previously retried (this is
a starvation prevention mechanism).
• A previously posted memory write to CSR space has not yet internally completed.
• The Configuration Lockout bit is set in the PXH_CONFIG register and the Intel® 6702PXH
64-bit PCI Hub is being configured locally after a cold boot sequence or during normal system
operation.
The Intel® 6702PXH 64-bit PCI Hub disconnects an initiator when one of the following conditions
is met:
• The Intel® 6702PXH 64-bit PCI Hub cannot accept any more write data.
• The Intel® 6702PXH 64-bit PCI Hub has no more read data to deliver.
• The memory address is non-linear.
• CSR memory reads and writes after the first data phase occur.
• Configuration reads and writes after the first data phase occur.
• The inverse decode window ends.
The Intel® 6702PXH 64-bit PCI Hub returns a target abort to the PCI bus when:
• The cycle master aborted or target aborted on the PCI Express bus (or the peer PCI bus for
Intel® 6702PXH 64-bit PCI Hub).
• Configuration reads and writes occur with address or data parity errors.
• CSR memory reads and writes occur with address or data parity errors.
Intel® 6702PXH 64-bit PCI Hub Datasheet
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