Signal Description
When one PCI bus segment is locked on the Intel® 6702PXH 64-bit PCI Hub the other is still free
to accept cycles, i.e. that bus is not locked. However, these cycles are not allowed to proceed on the
PCI Express bus or the locked PCI segment. Therefore, once the PCI bus is locked, no more cycles
will proceed onto the PCI Express bus from the non-locked PCI segment, or from the I/OxAPIC(s).
If during the LOCK sequence, any of the locked read commands results in a master or target abort
(either on the PCI bus or the internal switch interconnect), then the Intel® 6702PXH 64-bit PCI
Hub loses lock after sending a completion packet on the PCI Express bus. In the case of a memory
write receiving a target or master abort during a LOCK sequence, the Intel® 6702PXH 64-bit PCI
Hub only unlocks after the unlock message is received on the PCI Express bus. Outbound LOCK is
supported by the Intel® 6702PXH 64-bit PCI Hub.
Inbound LOCK transactions are treated with the LOCK signal ignored. Also locks to internal
devices, the SHPC, or the I/OxAPIC are not supported by the Intel® 6702PXH 64-bit PCI Hub.
See the summary in Table 2-23 for a summary of Intel® 6702PXH 64-bit PCI Hub responses to
LOCK transactions.
Table 2-23. LOCK Transaction Handling
End Point
Source
PCI
PCI Express*
SHPC Memory
I/OxAPIC
Ignore2
Ignore2
N/A
Error Reported1
Error Reported1
N/A
CSR Memory
PCI
N/A
Forward to PCI with PALOCK#
N/A
PCI Express*
Ignore2
NOTES:
1. For locked reads, a response of UR-EC is reported on the PCI Express* bus.
2. The transaction is treated as if it were a normal read or write transaction.
2.13
Hot Plug Controllers
The Intel® 6702PXH 64-bit PCI Hub hot plug controller allows PCI card removal, replacement,
and addition without powering down the system. The controller is compatible with the PCI
Standard Hot-Plug Controller and Subsystem Specification, Revision 1.0. The specification
includes two new register sets that are defined for the SHPC Capabilities List and the SHPC
Working Register Set. The new registers are defined as a PCI-PCI bridge capability in the
Intel® 6702PXH 64-bit PCI Hub and not as a separate PCI controller device. The new
specification also fixes the architectural proximity of the SHPC function to the PCI slots it controls.
The Intel® 6702PXH 64-bit PCI Hub may only control slots on its secondary bus(es) and there
must be a separate SHPC function associated with each of the logical PCI-PCI bridge configuration
spaces. The Standard Hot-Plug Controller in the Intel® 6702PXH 64-bit PCI Hub can control a
maximum of 6 slots in the system. It supports three to six PCI slots through an input/output serial
interface when operating in Serial Mode, and 1 to 2 slots through an input/output parallel interface
when operating in Parallel Mode. The input serial interface is polling and is in continuous
operation. The output serial interface is “demand” and acts only when requested. These serial
interfaces run at about 8.25 MHz regardless of the speed of the PCI bus. In parallel mode, the
Intel® 6702PXH 64-bit PCI Hub performs the serial to parallel conversion internally, so the serial
interface cannot be observed. However, internally the hot plug controller always operates in a serial
mode.
44
Intel® 6702PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
