Signal Description
2.12.5
Transaction Termination
2.12.5.1
PCI Mode Transaction Termination
2.12.5.1.1 Normal Master Termination
As a PCI master, the Intel® 6702PXH 64-bit PCI Hub uses normal termination if PADEVSEL# is
returned by the target within five clock cycles of PAFRAME# assertion. It terminates a transaction
when the following conditions are met:
• All write data for the transaction is transferred from the Intel® 6702PXH 64-bit PCI Hub data
buffers to the target.
• All read data for a read transaction have been transferred from the target to the
Intel® 6702PXH 64-bit PCI Hub.
• The master latency timer expires and the Intel® 6702PXH 64-bit PCI Hub’s bus grant is de-
asserted.
2.12.5.1.2 Master Abort Termination
If an Intel® 6702PXH 64-bit PCI Hub initiated transaction does not get a response with
PADEVSEL# within five clocks of PAFRAME# assertion, the Intel® 6702PXH 64-bit PCI Hub
terminates the transaction with a master abort. The Intel® 6702PXH 64-bit PCI Hub sets the
received master abort bit in the status register corresponding to the target bus. Read requests
(configuration, I/O, or memory) that receive master abort termination are sent back to the
PCI Express bus (or peer PCI bus for Intel® 6702PXH 64-bit PCI Hub) with a master abort status.
Delayed write requests that receive a master abort are sent back to PCI Express with master abort
status.
Note: When the Intel® 6702PXH 64-bit PCI Hub performs a Type 1 to special cycle translation, a master
abort is the expected termination for the special cycle on the target bus. In this case, the master
abort received bit is not set, and the Type 1 configuration transaction is disconnected after the first
data phase.
2.12.5.1.3 Target Termination Received by the Intel® 6702PXH 64-bit PCI Hub
If the Intel® 6702PXH 64-bit PCI Hub receives a target abort, and the cycle requires completion
on the PCI Express bus, the Intel® 6702PXH 64-bit PCI Hub will return the target abort status to
PCI Express. The Intel® 6702PXH 64-bit PCI Hub sets the received target abort status bit in the
secondary status register for all target aborts it receives on the PCI bus. Target abort can happen on
any data phase of a PCI-X transaction, and a read completion packet to PCI Express (or peer PCI
bus for Intel® 6702PXH 64-bit PCI Hub) incurring a target abort in the middle would return valid
data to the point of the target abort and a target abort completion status for the remainder.
2.12.5.1.4 Disconnect and Retry
If the Intel® 6702PXH 64-bit PCI Hub receives a disconnect response from a target, it will re-
initiate the transfer with the remaining length. When the Intel® 6702PXH 64-bit PCI Hub receives
a retry, it will wait at least two PCI clocks before it retries the transaction. If the retried transaction
is a write, the Intel® 6702PXH 64-bit PCI Hub will retry the write until it completes normally, or
with a target or master abort. If the retried transaction is a delayed read or delayed write
38
Intel® 6702PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
