Signal Description
• A CSR memory read or write occurs with address or data parity errors or attribute phase parity
errors.
All memory read cycles that cross the Intel® 6702PXH 64-bit PCI Hub receive a split transaction
termination, if they are not retried.
2.12.5.3
Intel® 6702PXH 64-bit PCI Hub Termination on Device Boundary
Crossing
On the PCI-X bus, any split request to the Intel® 6702PXH 64-bit PCI Hub that crosses a BAR
boundary (initial address + length > BAR limit) will result in a normal response up to the BAR
range and a “byte count out of range” response for the reminder of the length.
2.12.6
PCI-X Protocol Specifics
2.12.6.1
Attributes
Table 2-20 describes how the Intel® 6702PXH 64-bit PCI Hub fills in attribute fields where the
PCI-X bus specification leaves some implementation leeway.
Table 2-20. Intel® 6702PXH 64-bit PCI Hub Implementation of Requester Attribute Fields
Attribute
Function
No Snoop (NS)
The Intel® 6702PXH 64-bit PCI Hub just forwards this attribute in both directions
and does nothing with it internally.
Relaxed Ordering (RO)
This bit allows relaxed ordering of transactions, which the Intel® 6702PXH 64-bit
PCI Hub does not permit. This bit is simply forwarded in the Intel® 6702PXH 64-bit
PCI Hub, and is never generated on the PCI-X bus from a PCI Express* packet, or
vice-versa.
Tag
Since the Intel® 6702PXH 64-bit PCI Hub can have two outstanding requests on
the PCI-X bus at a time, this field can be either 0 or 1.
Byte Counts
This is based upon the length field from PCI Express, which is DWord-based.
2.12.6.2
2.12.6.3
4-Gbyte and 4-Kbyte Page Crossover
The PCI-X bus specification allows burst transactions to cross page (in the Intel® 6702PXH 64-bit
PCI Hub’s case, this is 4 Kbytes) and 4-Gbyte address boundaries. As a PCI-X bus master, the
Intel® 6702PXH 64-bit PCI Hub will always end the transaction at a 4-Kbyte boundary. As a
PCI-X bus target, the Intel® 6702PXH 64-bit PCI Hub will allow a burst past a 4-Kbyte page
boundary. Note that on the PCI Express bus, requests never cross a 4-Kbyte boundary on reads or
writes.
Wait States
The Intel® 6702PXH 64-bit PCI Hub will never generate wait states as a target except in the case
of CSR memory reads and configuration read and write accesses, which are handled with
immediate completions.
42
Intel® 6702PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
