Signal Description
2.12.3
Read Transactions
2.12.3.1
Prefetchable
Any memory read line or memory read multiple commands on the PCI bus that are decoded by the
Intel® 6702PXH 64-bit PCI Hub are prefetched on the PCI Express interface. The amount of data
prefetched depends on the clock frequency, PAREQ64#, and command type. The Intel® 6702PXH
64-bit PCI Hub does not prefetch past a 4-Kbyte page boundary.
2.12.3.2
2.12.3.3
Delayed
All memory read transactions are delayed read transactions. When the Intel® 6702PXH 64-bit PCI
Hub accepts a delayed read request, it samples the address, command, and address parity. This
information is entered into the delayed transaction queue. When in PCI-X mode, transactions
follow the split transaction model of PCI-X. Read data returned from PCI Express for an active
delayed transaction entry is forwarded to the PCI-X master as a split completion.
Internal CSR Space
Memory reads to internal CSR space are handled with an immediate completion on the PCI bus (in
both PCI and PCI-X modes). The Intel® 6702PXH 64-bit PCI Hub never asserts PAACK64# for
memory transactions to CSR space and hence CSR reads are 32-bit transactions. Reads to CSR
memory bypass the normal inbound queues towards PCI Express and complete on the PCI bus
within 16 PCI clocks. The Intel® 6702PXH 64-bit PCI Hub disconnects CSR memory reads after
the first data-phase, i.e. the Intel® 6702PXH 64-bit PCI Hub does not support PCI burst read
accesses to CSR memory space. Since the CSR space is non-prefetchable, only the bytes requested
within the DWord are returned.
Note: Since CSR reads bypass the PCI Express queues, semaphore reads to CSR space do not push
upstream writes that might contain the payload. In such cases, software must do a dummy read to
PCI Express to push the upstream writes.
2.12.4
Configuration Transactions
Type 0 configuration transactions are issued when the intended target resides on the same PCI bus
as the initiator. A Type 0 configuration transaction is identified by the configuration command and
the lowest 2 bits of the address set to 00b.
Type 1 configuration transactions are issued when the intended target resides on another PCI bus,
or when a special cycle is to be generated on another PCI bus. A Type 1 configuration command is
identified by the configuration command and the lowest 2 address bits set to 01b.
The register number is found in both Type 0 and Type 1 formats and gives the DWord address of
the configuration register to be accessed. The function number is also included in both Type 0 and
Type 1 formats and indicates which function of a multifunction device is to be accessed. For single-
function devices, this value is not decoded. Type 1 configuration transaction addresses also include
a 5-bit field designating the device number that identifies the device on the target PCI bus that is to
be accessed. In addition, the bus number in Type 1 transactions specifies the PCI bus to which the
transaction is targeted.
Intel® 6702PXH 64-bit PCI Hub Datasheet
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INTEL [ INTEL ]
