Register Description
Bits
Type
Reset
Description
10
RW
0
Interrupt Mask (INTMASK): This bit disables the SHPC from asserting
IRQ[23]# wired to the I/OxAPIC. This bit is valid only when the MSI is disabled;
i.e., the MSI enable bit (bit 0) in the MSC_MC register (offset 5Eh) is a zero. A
value of 0 for this bit enables the assertion of its IRQ[23]# signal to the
I/OxAPIC. A value of 1 disables the assertion of its IRQ[23]# signal.
If IRQ[23]# is already asserted when this bit is set, it must be de-asserted.
9
8
RO
0
0
Fast Back-to-Back Transactions Enable (FBTE): This bit has no meaning
on the PCI Express* interface. It is hardwired to ‘0’.
RW
SERR Enable (SEE): Controls the enable for PCI-compatible SERR reporting
on the PCI Express* interface (along with the Status Register (STS REG,
offset 06h, bit 14).
0 = Disable SERR reporting
1 = Enable SERR reporting
Note that this bit does not affect the setting of the PCI Express* error bits in the
PCI Express* Capability Structure.
7
6
RO
0
0
Wait Cycle Control (WCC): Reserved.
RW
Parity Error Response (PER): Controls the Intel® 6700PXH 64-bit PCI Hub
response to data parity errors forwarded from the PCI Express* interface and
peer PCI on read completions.
0 = Disable. The Intel® 6700PXH 64-bit PCI Hub ignores these errors on the
PCI Express* interface and the peer PCI interface.
1 = Enable. The Intel® 6700PXH 64-bit PCI Hub reports read completion data
parity errors on the PCI Express* interface and sets the Master Data Parity
Detected (MDPD) bit in the status register.
Note that this bit does not affect the setting of the PCI Express* error bits in the
PCI Express* Capability Structure.
5
4
RO
RO
0
0
VGA Palette Snoop (VGA_PS): Reserved.
Memory Write and Invalidate (MWI): The Intel® 6700PXH 64-bit PCI Hub
does not generate memory write and invalidate transactions, as the PCI
Express* interface does not have a corresponding transfer type.
3
2
RO
0
0
Special Cycle Enable (SCE): Reserved.
RW
Bus Master Enable (BME): Controls the Intel® 6700PXH 64-bit PCI Hub's
ability to issue memory and I/O read/write requests.
0 = Disable. The Intel® 6700PXH 64-bit PCI Hub cannot issue or I/O
read/write requests respond to any memory issue memory and I/O read/write
requests.
1 = Enable. The Intel® 6700PXH 64-bit PCI Hub can issue or I/O read/write
requests respond to any memory issue memory and I/O read/write requests.
1
0
RW
RW
0
0
Memory Space Enable (MSE): Controls the Intel® 6700PXH 64-bit PCI Hub's
response as a target to memory accesses on the PCI Express* interface that
address a device behind the Intel® 6700PXH 64-bit PCI Hub or the SHPC
memory space.
0 = These transactions are master aborted on the PCI Express* interface.
1 = The Intel® 6700PXH 64-bit PCI Hub is allowed to accept cycles from PCI
to be passed to the PCI Express* interface.
I/O Space Enable (IOSE): Controls the Intel® 6700PXH 64-bit PCI Hub's
response as a target to I/O transactions on the PCI Express* interface that
addresses a device that resides behind the Intel® 6700PXH 64-bit PCI Hub.
0 = These transactions are master aborted on the PCI Express* interface.
1 = Enables the Intel® 6700PXH 64-bit PCI Hub to respond to I/O transaction
initiated on the PCI Express* interface.
Intel® 6700PXH 64-bit PCI Hub Datasheet
85
INTEL [ INTEL ]
