Signal Description
• PCI Express* Reset – this is message coming on the PCI Express* interface and is not a
physical signal.
• Software PCI Reset – this reset is initiated by writing to bridge control register of the PCI
configuration space. This reset is specific to the particular bridge that the software wishes to
reset. This is also commonly referred to as the SBR (secondary bus reset).
• Hot plug Reset – This reset is caused by the act of writing to the command register with a
frequency change command.
2.17.2.1
PWROK Mechanism
All the voltage sources in the system are tracked by a system component that asserts the PWROK
signal only after all the voltages have been stable for some predetermined time. The
Intel® 6700PXH 64-bit PCI Hub receives the PWROK signal as an asynchronous input, meaning
that there is no assumed relationship between the assertion or the de-assertion of PWROK and the
reference clock. While the PWROK is de-asserted the Intel® 6700PXH 64-bit PCI Hub will hold
all logic in reset.
The PWROK reset will clear all internal state machines and logic, and initialize all registers to their
default states including ‘sticky’ error bits that are persistent through all other reset classes. To
eliminate potential system reliability problems, all devices are also required to either tristate their
outputs or to drive them to safe levels during such a power on reset.
Refer to the PCI Express* specification for details of the relationship between PWROK assertion
and the clocks and power being stable at the input of the Intel® 6700PXH 64-bit PCI Hub.
For the Intel® 6700PXH 64-bit PCI Hub in PCI-X Mode 1, PxPCIRST# is asserted for 2 ms after
PWROK goes high.
2.17.2.2
RSTIN# Mechanism
Once the system is up and running, a full system reset may be required to recover from system
error conditions related to various device or subsystem failures. This hot reset mechanism is
provided to accomplish this recovery without clearing the ‘sticky’ error status bits useful to track
the cause of the device or subsystem error conditions.
A hot reset can be initiated by asserting the RSTIN# signal. This signal is treated as an
asynchronous input to the Intel® 6700PXH 64-bit PCI Hub, meaning that there is no assumed
relationship between the assertion or the de-assertion of RSTIN# and the host reference clock.
Board designers must design this RSTIN# pin asserted period comprehending potential mode
switches that can happen on the PCI-X bus and the associated time period required to settle the
voltage and meeting the minimum PxPCIRST# timing requirements. This could be up to or beyond
320 ms.
2.17.2.3
PCI Express* Reset Mechanism
There is no reset signal on the PCI Express* bus, as all reset communication is in-band. The north
PCI Express* device (such as an MCH) communicates the fact that it is entering and coming out of
a reset using messages. The Intel® 6700PXH 64-bit PCI Hub will respond by also going through a
reset. This incoming message by nature of the PCI Express* protocol is asynchronous to the
reference clock. However, when the Intel® 6700PXH 64-bit PCI Hub goes through a reset for its
own reasons (PWROK, RSTIN#) the link goes down, which will be inferred by the north device
and handled with a hot plug reset (if hot plug is enabled).
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Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
