Signal Description
2.18
Reliability, Availability, and Serviceability (RAS)
The Intel® 6700PXH 64-bit PCI Hub provides the RAS features listed below to serve the needs of
enterprise class servers and telecommunication blade applications.
2.18.1
PCI Express* Error Handling
The PCI Express* link in the Intel® 6700PXH 64-bit PCI Hub is 32-bit CRC protected providing
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for very high reliability. With a target bit error rate of 10 the 32-bit CRC combined with the
8b/10b encoding on the serial link, provides for greater than 10 years in MTBF (mean time
between failure). The smaller link packets will utilize a 16-bit CRC scheme. PCI Express* also
provides for a software-transparent recovery from temporary link failures. When received packets
are in error, hardware could automatically retransmit the packet. In case of permanent link failure,
the link can reconfigure itself for a narrower width and for a lower performance operation. The
Intel® 6700PXH 64-bit PCI Hub supports this downgraded operation from X8 to X4.
2.18.2
2.18.3
PCI Error Protection
PCI buses are parity protected. Upper and lower 32 bits on the PCI bus are separately parity
protected.
PCI Standard Hot Plug Controller
The Intel® 6700PXH 64-bit PCI Hub supports the PCI Standard Hot-Plug Controller and
Subsystem Specification Revision 1.0, which allows PCI cards to be hot added or removed without
bringing down the system.
2.18.4
SMBus
The Intel® 6700PXH 64-bit PCI Hub supports full access to the Intel® 6700PXH 64-bit PCI Hub
configuration and memory space from the SMBus for system debug and management.
2.19
Error Handling
When integrity errors occur on the PCI or PCI Express* buses, the Intel® 6700PXH 64-bit PCI
Hub implements the specified error logging and escalation actions as per the interface rules. For
example, errors encountered on the PCI interface follow the logging and escalation rules of the PCI
protocol. Beyond the set of escalation and error logging mandated by the interface specifications,
the Intel® 6700PXH 64-bit PCI Hub also implements some chipset-specific error logging and
escalation mechanisms to aid system software/driver in a more graceful error recovery and also for
system debug.
The error escalation mechanism implemented by the Intel® 6700PXH 64-bit PCI Hub can be fully
masked. This provides the platform software with the ability to pick and choose what it wants to do
on any of the error conditions. All Intel® 6700PXH 64-bit PCI Hub-specific logging registers are
sticky, that is, these registers retain their values through any chip reset other than a power cycle
reset.
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Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
