Signal Description
2.12.11 Assumptions and Intel® 6700PXH 64-bit PCI Hub
Requirements
2.12.11.1 MRL Opening during the Sequence
While executing an enable or disable sequence, if the MRL of one of the cards is opened then the
Intel® 6700PXH 64-bit PCI Hub performs the auto power down for that slot after executing the
current enable/disable operation. As the maximum time required to enable is disable is 319 ms, the
maximum delay between MRL open and auto-power down would be less than 320 ms.
2.12.11.2 Power Fault
The power controller/slot control logic is responsible for removing power from the slot and
isolating the card in the event of a power fault. The Intel® 6700PXH 64-bit PCI Hub would notify
software in the event of a power fault and wait for the slot disable command from the software to
disable the appropriate slot.
2.13
Addressing
2.13.1
I/O Window Addressing
I/O accesses from the PCI Express* bus always target the PCI bus. No I/O accesses are allowed
from PCI to PCI Express* and nor are any I/O accesses to internal devices (APIC, CSR, SHPC)
allowed.
2.13.1.1
Mode I/O Access
One I/O window can be set up for forwarding I/O transactions from the PCI Express* to the PCI
bus. No I/O transactions can be forwarded from the PCI to the PCI Express* bus. The registers and
register bits listed below define the setup and control of this I/O window:
• I/O Base and Limit Address Registers
• I/O Enable bit in the Command Register
• Enable 1-Kbyte granularity in the Intel® 6700PXH 64-bit PCI Hub Configuration Register
To enable outbound I/O transactions, the I/O Enable bit (bit 0) must be set in the PD_CMD
Register in the Intel® 6700PXH 64-bit PCI Hub configuration space (offset 04–05h). If the I/O
Enable bit is not set, all I/O transactions initiated on the PCI Express* interface will receive a
master abort completion. No inbound I/O transactions may cross the bridge and are therefore
master aborted.
The Intel® 6700PXH 64-bit PCI Hub implements one set of I/O Base and Limit Address Registers
in configuration space that define an I/O address range for the bridge. PCI Express* interface I/O
transactions with addresses that fall inside the range defined by the I/O Base and Limit Address
Registers are forwarded to PCI, and PCI I/O transactions with addresses that fall outside this range
are master aborted.
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Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
