Signal Description
In each of these cases, the Intel® 6700PXH 64-bit PCI Hub will drive the PxM66EN pin to GND
for the affected PCI bus. However, it should be noted that when the Intel® 6700PXH 64-bit PCI
Hub is in 1-Slot mode and the slot is disconnected, the Intel® 6700PXH 64-bit PCI Hub will never
drive the PxM66EN pin. This is to allow the hot plug controller the ability to correctly sample the
M66EN pin on the PCI slot when the PCI bus is grounded (not connected) but the PCI card is
powered on. In this mode, it is recommended that the M66EN pin be pulled up to the PCI slot's
3.3V power rail, which is controlled by the hot plug controller.
2.12.9
Hot Plug Interrupts
2.12.9.1
MSI and Pin Interrupts
SHPC in the Intel® 6700PXH 64-bit PCI Hub can either be enabled to generate an MSI interrupt or
can generate an interrupt to the internal I/OxAPIC to be routed through it to the MCH. The SHPC
interrupt is routed to interrupt input 23 of the I/OxAPIC. These two interrupts are mutually
exclusive. The message for MSI comes from the message address and data registers in the
Intel® 6700PXH 64-bit PCI Hub’s MSI capability registers. The message enable bit in the message
control register of the capability registers either enables MSI or interrupt routing through
I/OxAPIC.
2.12.9.2
ACPI Support
On platforms where the platform ACPI-compliant firmware controls the SHPC rather than having
native-OS support for the SHPC, the SHPC interrupts need to be converted to an ACPI interrupt
(that goes to an SCI interrupt to the processor). In the presence of native OS-support, this interrupt
steering is not needed. In previous platforms where hot plug was firmware controlled, this was
done by converting the hot plug interrupt into a side-band pin interrupt which was then directly
routed to the GPE# pin in the ICH. In Intel® 6700PXH 64-bit PCI Hub systems, an in-band
message is generated via the PCI Express* interface. The interrupt steering is controlled through a
BIOS-specific bit SGME (bit 5 in CNF). This bit programs the hot plug controller to generate an
SCI message to MCH instead of an MSI or a pin interrupt to the internal I/OxAPIC. This SCI
message is ultimately routed by MCH to the ICH via the GPE# pin. On assertion of the GPE# pin
to the ICH, the ICH pulls the SCI pin to the processor, which in turn wakes up the ACPI handler.
All logic in the SHPC function is the same as for normal MSI or pin interrupts.
2.12.10 Error Handling
The standard hot-plug controller can detect a variety of error conditions (refer to the PCI Standard
Hot-Plug Controller and Subsystem Specification Revision 1.0 for details) and it can be
programmed to either send an error message on the PCI Express* interface or raise an interrupt.
Intel® 6700PXH 64-bit PCI Hub Datasheet
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