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6700PXH 参数 Datasheet PDF下载

6700PXH图片预览
型号: 6700PXH
PDF下载: 下载PDF文件 查看货源
内容描述: 64位PCI中枢 [64-bit PCI Hub]
分类和应用: PC
文件页数/大小: 194 页 / 2283 K
品牌: INTEL [ INTEL ]
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Signal Description  
2.12.7  
Initialization  
2.12.7.1  
In-box Architecture  
With the in-box solution it is assumed that Intel® 6700PXH 64-bit PCI Hub would be an  
embedded part of the system board and the system BIOS has complete knowledge of the PCI buses  
below the Intel® 6700PXH 64-bit PCI Hub, like the loading characteristics of the bus, the slot  
numbering scheme on the bus, etc. In such an architecture, whenever the SHPC in the Intel®  
6700PXH 64-bit PCI Hub is initialized (power-on or a PCI Express* bus reset) the system  
BIOS/firmware is invoked to initialize the SHPC working register set with board-specific  
information (HWInit Registers) and also initialize the PCI bus beneath Intel® 6700PXH 64-bit PCI  
Hub to the proper mode and frequency. Whenever the standard hot plug controller is reset, the slot  
interface outputs are reset to the following:  
PCIRST# is asserted.  
BUSEN# is de-asserted (disconnected from the bus).  
CLKEN# is de-asserted (PCI clock disconnected from the bus).  
PWREN is de-asserted (slot power is removed).  
All PWRLED# and ATNLED# outputs are set to OFF.  
When HPx_SLOT[3] for a PCI interface is “1” (hot plug is enabled), then whenever the SHPC is  
initialized, the PCI bus will power up operating at 33 MHz PCI and all hot plug slots isolated from  
the bus. The platform BIOS/firmware could later determine the capabilities of the non-hot plug PCI  
cards (reading the PCI-X and 66 MHz capability bits in the PCI register space of the cards) and  
also the capabilities of the inserted hot plug cards, for PCI-X capability, or PCI capability at  
66 MHz, and then could reset the PCI bus to operate in the new mode. The software could execute  
a set bus frequency/mode command to achieve the mode.  
2.12.7.2  
Remote-I/O-Box Architecture  
This architecture is characterized by routing the hot plug interrupt to a generic interrupt pin as  
described in the PCI Standard Hot-Plug Controller and Subsystem Specification Revision 1.0.  
When the OS detects the SHPC in a peer-to-peer bridge, it is required by the specification to run  
the OSHP ACPI control method. The code that initializes the SHPC registers can be placed in the  
control method. Refer to Section 5.5.1 of the PCI Standard Hot-Plug Controller and Subsystem  
Specification, Revision 1.0 for more details on the OSHP method.  
2.12.8  
M66EN Pin Handling  
The Intel® 6700PXH 64-bit PCI Hub can drive the PxM66EN pin on each PCI bus to GND in  
Serial mode and in 2-Slot parallel mode. There are three possible cases where the Intel® 6700PXH  
64-bit PCI Hub will drive the PxM66EN pin:  
The PFREQ and PMODE registers are reprogrammed for 33-MHz PCI mode and a secondary  
bus reset is completed.  
The Intel® 6700PXH 64-bit PCI Hub is powered on with any Hot Plug mode enabled by  
strapping the HPx_SLOT[3] pin to “1” at the rising edge of PWROK.  
A change frequency/mode command is executed by the standard hot plug controller with the  
frequency set at 33 MHz.  
54  
Intel® 6700PXH 64-bit PCI Hub Datasheet