Signal Description
• The Configuration Lockout bit is set in the PXH_CONFIG register and the Intel® 6700PXH
64-bit PCI Hub is being configured locally after a cold boot sequence or during normal system
operation.
The Intel® 6700PXH 64-bit PCI Hub disconnects an initiator when one of the following conditions
is met:
• The Intel® 6700PXH 64-bit PCI Hub cannot accept any more write data.
• The Intel® 6700PXH 64-bit PCI Hub has no more read data to deliver.
• The memory address is non-linear.
• CSR memory reads and writes after the first data phase occur.
• Configuration reads and writes after the first data phase occur.
• The inverse decode window ends.
The Intel® 6700PXH 64-bit PCI Hub returns a target abort to the PCI bus when:
• The cycle master aborted or target aborted on the PCI Express* bus or the peer PCI bus.
• Configuration reads and writes occur with address or data parity errors.
• CSR memory reads and writes occur with address or data parity errors.
2.11.5.2
PCI-X Mode Transaction Termination
2.11.5.2.6
Initiator Disconnect or Satisfaction of Byte Count
As a PCI-X master, the Intel® 6700PXH 64-bit PCI Hub uses normal termination (initiator
disconnect or satisfaction of byte count) if PxDEVSEL# is returned by the target within six clock
cycles after the address phase. The Intel® 6700PXH 64-bit PCI Hub terminates a transaction when
one of the following conditions are met:
• All write data indicated in the byte count of the write transaction is transferred from
Intel® 6700PXH 64-bit PCI Hub data buffers to the target. The Intel® 6700PXH 64-bit PCI
Hub never does an initiator disconnect on a write before the byte count size has been satisfied.
• An initiator disconnect occurs at the next ADB on a split read completion because the
Intel® 6700PXH 64-bit PCI Hub data buffer has run dry.
• An initiator disconnect at the next ADB when the master latency timer has expired and the
Intel® 6700PXH 64-bit PCI Hub’s bus grant signal is de-asserted.
2.11.5.2.7
Master Abort Termination
If a Intel® 6700PXH 64-bit PCI Hub initiated transaction is not responded to with PxDEVSEL#
within six clocks after address phase, the Intel® 6700PXH 64-bit PCI Hub terminates the
transaction with a master abort. The Intel® 6700PXH 64-bit PCI Hub sets the received master
abort bit in the secondary status register. Read requests (configuration, I/O, memory) that receive
master abort termination are sent back to PCI Express* / peer PCI with a master abort status.
Delayed write requests that receive master abort are sent back to PCI Express* with a master abort
status.
Note: When the Intel® 6700PXH 64-bit PCI Hub performs a Type 1 to special cycle translation, a master
abort is the expected termination for the special cycle on the target bus. In this case, the master
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Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
