Signal Description
the first data-phase, i.e. the Intel® 6700PXH 64-bit PCI Hub does not support PCI burst read
accesses to CSR memory space. Since the CSR space is non-prefetchable, only the bytes requested
within the DWord are returned.
Note: Since CSR reads bypass the PCI Express* queues, semaphore reads to CSR space do not push
upstream writes that might contain the payload. In such cases, software must do a dummy read to
PCI Express* to push the upstream writes.
2.11.4
Configuration Transactions
Type 0 configuration transactions are issued when the intended target resides on the same PCI bus
as the initiator. A Type 0 configuration transaction is identified by the configuration command and
the lowest 2 bits of the address set to 00b.
Type 1 configuration transactions are issued when the intended target resides on another PCI bus,
or when a special cycle is to be generated on another PCI bus. A Type 1 configuration command is
identified by the configuration command and the lowest 2 address bits set to 01b.
The register number is found in both Type 0 and Type 1 formats and gives the DWord address of
the configuration register to be accessed. The function number is also included in both Type 0 and
Type 1 formats and indicates which function of a multifunction device is to be accessed. For single-
function devices, this value is not decoded. Type 1 configuration transaction addresses also include
a 5-bit field designating the device number that identifies the device on the target PCI bus that is to
be accessed. In addition, the bus number in Type 1 transactions specifies the PCI bus to which the
transaction is targeted.
2.11.5
Transaction Termination
PCI Mode Transaction Termination
Normal Master Termination
2.11.5.1
2.11.5.1.1
As a PCI master, the Intel® 6700PXH 64-bit PCI Hub uses normal termination if PxDEVSEL# is
returned by the target within five clock cycles of PxFRAME# assertion. It terminates a transaction
when the following conditions are met:
• All write data for the transaction is transferred from the Intel® 6700PXH 64-bit PCI Hub data
buffers to the target.
• All read data for a read transaction have been transferred from the target to the Intel®
6700PXH 64-bit PCI Hub.
• The master latency timer expires and the Intel® 6700PXH 64-bit PCI Hub’s bus grant is de-
asserted.
2.11.5.1.2
Master Abort Termination
If a Intel® 6700PXH 64-bit PCI Hub initiated transaction does not get a response with
PxDEVSEL# within five clocks of PxFRAME# assertion, the Intel® 6700PXH 64-bit PCI Hub
terminates the transaction with a master abort. The Intel® 6700PXH 64-bit PCI Hub sets the
received master abort bit in the status register corresponding to the target bus. Read requests
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Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
