Signal Description
The Intel® 6700PXH 64-bit PCI Hub never retries a completion since it always has enough buffer
space for all split requests it sends out. No transaction information is retained on any writes.
The Intel® 6700PXH 64-bit PCI Hub disconnects an initiator when one of the following conditions
is met:
• The Intel® 6700PXH 64-bit PCI Hub cannot accept any more write data and an ADB is
reached.
• A split completion packet is being sent, an ADB is reached, and the Intel® 6700PXH 64-bit
PCI Hub read buffers are running dry.
• A CSR memory read or write occurs after the first data phase.
• The inversed decode window ends and an inbound write is in progress, regardless of write
buffer availability.
The Intel® 6700PXH 64-bit PCI Hub returns a target abort to PCI when:
• A split completion packet is sent to a PCI-X agent and the split cycle target aborted on the
PCI Express* bus or peer PCI bus.
• A configuration read or write occurs with address or data parity errors or attribute phase parity
errors.
• A CSR memory read or write occurs with address or data parity errors or attribute phase parity
errors.
All memory read cycles that cross the Intel® 6700PXH 64-bit PCI Hub receive a split transaction
termination, if they are not retried.
2.11.5.3
Intel® 6700PXH 64-bit PCI Hub Termination on
Device Boundary Crossing
On the PCI-X bus, any split request to the Intel® 6700PXH 64-bit PCI Hub that crosses a BAR
boundary (initial address + length > BAR limit) will result in a normal response up to the BAR
range and a “byte count out of range” response for the reminder of the length.
2.11.6
PCI-X Protocol Specifics
2.11.6.1
Attributes
Table 2-19 describes how the Intel® 6700PXH 64-bit PCI Hub fills in attribute fields where the
PCI-X bus specification leaves some implementation leeway.
Table 2-19. Intel® 6700PXH 64-bit PCI Hub Implementation of Requester Attribute Fields
(Sheet 1 of 2)
Attribute
No Snoop (NS)
Function
The Intel® 6700PXH 64-bit PCI Hub just forwards this attribute in both directions
and does nothing with it internally.
Relaxed Ordering (RO)
This bit allows relaxed ordering of transactions, which the Intel® 6700PXH 64-bit
PCI Hub does not permit. This bit is simply forwarded in the Intel® 6700PXH
64-bit PCI Hub, and is never generated on the PCI-X bus from a PCI Express*
packet, or vice-versa.
44
Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
