Signal Description
(configuration, I/O, or memory) that receive master abort termination are sent back to the
PCI Express* bus or peer PCI bus with a master abort status. Delayed write requests that receive a
master abort are sent back to PCI Express* with master abort status.
Note: When the Intel® 6700PXH 64-bit PCI Hub performs a Type 1 to special cycle translation, a master
abort is the expected termination for the special cycle on the target bus. In this case, the master
abort received bit is not set, and the Type 1 configuration transaction is disconnected after the first
data phase.
2.11.5.1.3
Target Termination Received by the Intel® 6700PXH 64-bit PCI Hub
If the Intel® 6700PXH 64-bit PCI Hub receives a target abort, and the cycle requires completion
on the PCI Express* bus, the Intel® 6700PXH 64-bit PCI Hub will return the target abort status to
PCI Express*. The Intel® 6700PXH 64-bit PCI Hub sets the received target abort status bit in the
secondary status register for all target aborts it receives on the PCI bus. Target abort can happen on
any data phase of a PCI-X transaction, and a read completion packet to PCI Express* or peer PCI
bus incurring a target abort in the middle would return valid data to the point of the target abort and
a target abort completion status for the remainder.
2.11.5.1.4
Disconnect and Retry
If the Intel® 6700PXH 64-bit PCI Hub receives a disconnect response from a target, it will re-
initiate the transfer with the remaining length. When the Intel® 6700PXH 64-bit PCI Hub receives
a retry, it will wait at least two PCI clocks before it retries the transaction. If the retried transaction
is a write, the Intel® 6700PXH 64-bit PCI Hub will retry the write until it completes normally, or
with a target or master abort. If the retried transaction is a delayed read or delayed write
transaction, the Intel® 6700PXH 64-bit PCI Hub will allow memory reads and writes to pass the
transaction. A retry is not considered an error condition, and so there is no error logging or
reporting done on a retry.
2.11.5.1.5
Target Termination Initiated by the Intel® 6700PXH 64-bit PCI Hub
The Intel® 6700PXH 64-bit PCI Hub returns a target retry to an initiator when any of the following
conditions is met:
• A new memory read transaction occurs and the Intel® 6700PXH 64-bit PCI Hub delayed
transaction queue is full.
• A memory read occurs that has already been queued, but has not completed on the
PCI Express* bus.
• A memory read occurs that has been queued and completed on the PCI Express* bus but
ordering rules require an outbound posted write to complete ahead of it.
• A memory read or write to CSR space occurs and a previously posted write to CSR space has
not yet internally completed.
• A LOCK transaction is established from the PCI Express* to the PCI bus.
• A memory write transaction occurs and the Intel® 6700PXH 64-bit PCI Hub has no free
buffer space to accept the write.
• A memory write occurs from a master other than the master that was previously retried (this is
a starvation prevention mechanism).
• A previously posted memory write to CSR space has not yet internally completed.
Intel® 6700PXH 64-bit PCI Hub Datasheet
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INTEL [ INTEL ]
