Signal Description
Table 2-19. Intel® 6700PXH 64-bit PCI Hub Implementation of Requester Attribute Fields
(Sheet 2 of 2)
Attribute
Function
Tag
Since the Intel® 6700PXH 64-bit PCI Hub can have two outstanding requests on
the PCI-X bus at a time, this field can be either 0 or 1.
Byte Counts
This is based upon the length field from PCI Express*, which is DWord-based.
2.11.6.2
4-Gbyte and 4-Kbyte Page Crossover
The PCI-X bus specification allows burst transactions to cross page (in the Intel® 6700PXH 64-bit
PCI Hub’s case, this is 4 Kbytes) and 4-Gbyte address boundaries. As a PCI-X bus master, the
Intel® 6700PXH 64-bit PCI Hub will always end the transaction at a 4-Kbyte boundary. As a
PCI-X bus target, the Intel® 6700PXH 64-bit PCI Hub will allow a burst past a 4-Kbyte page
boundary. Note that on the PCI Express* bus, requests never cross a 4-Kbyte boundary on reads or
writes.
2.11.6.3
2.11.6.4
Wait States
The Intel® 6700PXH 64-bit PCI Hub will never generate wait states as a target except in the case
of CSR memory reads and configuration read and write accesses, which are handled with
immediate completions.
Split Transactions
2.11.6.4.12 Completer Attributes
Table 2-20. Intel® 6700PXH 64-bit PCI Hub Implementation Completion Attribute Fields
Attribute
Function
Byte Count Modified (BCM)
The Intel® 6700PXH 64-bit PCI Hub sets this bit only in NT mode
when the burst read starts from within 3 data phases of the BAR
boundary and crosses the BAR boundary.
Split Completion Error (SCE)
The Intel® 6700PXH 64-bit PCI Hub will only set this bit if a memory
read command from PCI-X master or target aborted on the PCI
Express* bus, and also for byte count out-of-range error in NT mode.
Split Completion Message (SCM)
This bit shadows the SCE bit.
2.11.6.4.13 Requirements for Accepting Split Completions
The Intel® 6700PXH 64-bit PCI Hub asserts PxDEVSEL# and discards the data if the Requester
ID matches the bridge, but the tag does not match that of any outstanding requests from this device.
2.11.6.4.14 Split Completion Messages
The Intel® 6700PXH 64-bit PCI Hub can only generate error messages for cycles that cross the
bridge and which master or target abort. No DWord cycles that require completion (i.e. I/O cycles)
will cross the bridge. Therefore, the Intel® 6700PXH 64-bit PCI Hub can only generate a “PCI-X
Bridge Error” completion message for the memory read commands as indicated in Table 2-21.
Intel® 6700PXH 64-bit PCI Hub Datasheet
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INTEL [ INTEL ]
