Signal Description
abort received bit is not set, and the Type 1 configuration transaction is disconnected after the first
data phase.
2.11.5.2.8
Target Termination Received by the Intel® 6700PXH 64-bit PCI Hub
If the Intel® 6700PXH 64-bit PCI Hub receives a target abort, and the cycle requires completion
on the PCI Express* bus, the Intel® 6700PXH 64-bit PCI Hub will return the target abort status to
PCI Express*. The Intel® 6700PXH 64-bit PCI Hub sets the received target abort status bit in the
secondary status register for all target aborts it receives on the PCI bus. Target abort can happen on
any data phase of a PCI-X transaction, and a read completion packet to PCI Express* / peer PCI,
incurring a target abort in the middle of the packet would return valid data to the point of target
abort and all 1s for the reminder of the length and a target abort completion status for the entire
packet.
2.11.5.2.9
Disconnect and Retry
If the Intel® 6700PXH 64-bit PCI Hub receives a disconnect response (single data phase or at next
ADB) from a target, it will re-initiate the transfer with the remaining length. When the
Intel® 6700PXH 64-bit PCI Hub receives a retry, it will wait at least two PCI clocks before it
retries the transaction. If the retried transaction is a write, the Intel® 6700PXH 64-bit PCI Hub will
retry the write till it completes normally or with a target or master abort. If the retried transaction is
a delayed read or delayed write transaction, the Intel® 6700PXH 64-bit PCI Hub will allow
memory reads, split completions and writes to pass the transaction. A retry is not considered an
error condition and so there is no error logging or reporting done on a retry.
2.11.5.2.10 Split Response
The Intel® 6700PXH 64-bit PCI Hub can receive split response for memory reads, I/O and
configuration read and write transactions.
2.11.5.2.11 Target Termination Initiated by the Intel® 6700PXH 64-bit PCI Hub
The Intel® 6700PXH 64-bit PCI Hub returns a target retry to an initiator when any of the following
conditions is met:
• A new memory read transaction and the Intel® 6700PXH 64-bit PCI Hub delayed transaction
queue is full.
• A memory read or write to CSR space and a previously posted write to CSR space has not yet
internally completed.
• A LOCK transaction has been established from PCI Express* to PCI.
• A memory write transaction and the Intel® 6700PXH 64-bit PCI Hub has no free buffer space
to accept the write.
• A memory write is from a master other than the master that was previously retried (starvation
prevention mechanism).
• A configuration transaction to the secondary configuration space and a previously posted
memory write to CSR space has not yet internally completed.
• The Configuration Lockout bit is set in the PXH_CONFIG register and the Intel® 6700PXH
64-bit PCI Hub is being configured locally after a cold boot sequence or during normal system
operation.
Intel® 6700PXH 64-bit PCI Hub Datasheet
43
INTEL [ INTEL ]
