Register Description
3.8.2.5
Offset 40h: EOI—End of Interrupt (EOI) Register
Offset:
Default Value: xxh
40h
Attribute: WO
Size: 8 bits
The EOI register is present to provide a mechanism to maintain the level triggered semantics for
level-triggered interrupts issued on the parallel bus.
When a write is issued to this register, the I/OxAPIC will check the lower 8 bits written to this
register, and compare it with the vector field for each entry in the I/O Redirection Table. When a
match is found, the Remote_IRR bit for that I/O Redirection Entry is cleared.
Note that if multiple I/O Redirection entries, for any reason, assign the same vector for more than
one interrupt input, each of those entries will have the Remote_IRR bit reset to ‘0’.
Bits
Type
Reset
Description
7:0
WO
xxh
End of Interrupt (EOI): Vector to be cleared by the EOI.
3.8.3
Indirect Memory Space Registers
3.8.3.1
Register Summary
To access the indirect memory space, an 8-bit value must be written to the index register, which is
a “pointer” (indirect) to a 32-bit memory location. The 32-bit value in the Window Register can
then be read.
Table 3-4. Indirect Memory Space Registers Summary
Address
Offset
Symbol
Full Name
Default
Attribute
00h
01h
03h
10h
11h
ID
APIC ID Register
00000000h
00178020h
00000001h
00010000h
00000000h
00010000h
00000000h
00000000h
RW, RO
RO
VS
Version Register
BCFG
Boot Configuration Register
Redirection Table Low DWord 0 Register
Redirection Table High DWord 0 Register
Redirection Table Low DWord 23 Register
Redirection Table High DWord 23 Register
Reserved.
RW, RO
RW, RO
RW, RO
RW, RO
RW, RO
RO
RDL[0]
RDH[0]
RDL[23]
RDH[23]
Reserved
3E
3F
40–FF
Intel® 6700PXH 64-bit PCI Hub Datasheet
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INTEL [ INTEL ]
