Register Description
3.8.1.27
Offset 6Eh: PM_CAP – Power Management Capabilities
Register (D0: F1, F3)
Offset:
Default Value: 0002h
6Eh
Attribute: RO
Size: 16 bits
Bits
Type
Reset
Description
15:3
2:0
RO
RO
0
Reserved.
10b
Version (VERS): I/OxAPIC Power Management implementation is compliant
with the PCI PM Specification Revision 1.1.
3.8.1.28
Offset 70h: PM_CNTLSTS – Power Management Control
and Status Register (D0: F1, F3)
Offset:
Default Value: 0000h
70h
Attribute: RW, RO
Size: 16 bits
This register provides information about PCI Express* link specific parameters.
Bits
Type
Reset
Description
15:2
1:0
RO
0
0
Reserved.
RW
PowerState (PWR_ST): This 2-bit field is used both to determine the current
power state of a function and to set the function into a new power state. The
I/OxAPIC supported field values are given below.
00b – D0
01b – Reserved
10b – Reserved
11b – D3hot
If software attempts to write an unsupported, optional state to this field, the
write operation must complete normally on the bus; however, the data is
discarded and no state change occurs. When in D3hot state, the I/OxAPIC
responds to configuration transactions only and a transition from D3hot to D0
does not reset the I/OxAPIC’s registers. Also, in D3hot state, the I/OxAPIC
cannot generate any MSI. Virtual wire interrupts generated by the I/OxAPIC on
behalf of PCI agents/SHPC are not masked by the D3hot state.
3.8.2
I/OxAPIC Direct Memory Space Registers
3.8.2.1
Register Summary
Offset
Address
Symbol
Full Name
Default
Attribute
00h
10–13h
20h
IDX
WND
PAR
EOI
Index Register
00h
RW
RW
Window Register
IRQ Pin Assertion Register
EOI Register
00000000h
000000xxh
xxh
RW, RO
WO
40h
Intel® 6700PXH 64-bit PCI Hub Datasheet
151
INTEL [ INTEL ]
