Register Description
3.8.1.24
Offset 56h LSTS—Link Status Register (D0:F1, F3)
Offset:
56-57h
Attribute: RO
Size: 16 bits
Default Value: 0001h (X1 Link)
0041h (X4 Link)
0081h (X8 Link)
This register provides information about PCI Express* link specific parameters.
Bits
Type
Reset
Description
15:10
9:4
RO
RO
0
Reserved.
0h, 4h,
or 8h
Negotiated Link Width (NLW): Indicates the negotiated width of PCI
Express* Link. Defined encodings are:
000000b X1 width
000100b X4 width
001000b X8 width
3:0
RO
1h
Link Speed (LS): Intel® 6700PXH 64-bit PCI Hub supports a PCI Express*
link speed of 2.5 Gbps only, so this field is set to the PCI-SIG defined value for
2.5 Gbps, which is 0001b, or 1h.
3.8.1.25
Offset 6Ch: PM_CAPID – Power Management Capability
Identifier Register (D0:F1, F3)
Offset:
Default Value: 00h
6Ch
Attribute: RO
Size: 8 bits
This register provides information about PCI Express* link specific parameters.
Bits
Type
Reset
Description
7:0
RO
01h
Capability ID (CAP_ID): Capability ID indicates PCI compatible Power
Management.
3.8.1.26
Offset 6Dh: PM_NXTPTR – Power Management Next Pointer
Offset:
Default Value: 00h
6Dh
Attribute: RO
Size: 8 bits
This register provides information about PCI Express* link specific parameters.
Bits
Type
Reset
Description
7:0
RO
0
Next Pointer (NXTPTR): Next Pointer if non-zero.
150
Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
