Register Description
3.8.1.23
Offset 54h: LCTL—Link Control Register (D0:F1, F3)
Offset:
Default Value: 0000h
54-55h
Attribute: RW; RO
Size: 16 bits
This register controls PCI Express* link specific parameters.
Bits
Type
Reset
Description
15:7
6
RO
0
0
Reserved.
RW
Common Clock Configuration (CCC): This bit when set indicates that Intel®
6700PXH 64-bit PCI Hub and the component it is connected to via the PCI
Express* link (located at the opposite end of this link) are operating with a
distributed common reference clock. A value of 0 indicates that this
component and the component at the opposite end of this Link are operating
with an asynchronous reference clock.
0 = Intel® 6700PXH 64-bit PCI Hub and the other PCI Express* component
have an asynchronous reference clock
1 = Intel® 6700PXH 64-bit PCI Hub and the other PCI Express* component
share a common clock
Note that this bit is used to reflect the proper L0s exit latency value in the
EXP_LSTS register.
5:4
3
RO
RO
0
0
Reserved.
Read Request Return Parameter Control (RRRPC): Not used by the
I/OxAPIC.
2
RO
0
0
Reserved.
1:0
RW
Active State Link PM Control (ASLPMC): Controls the level of active state
Power Management supported on the given PCI Express* link. The PCI-SIG
defined encodings are as follows:
00b Disabled
01b L0s entry supported
10b Reserved
11b L0s and L1s entry supported
These bits enable Intel® 6700PXH 64-bit PCI Hub to enter L0s. Not used by
I/OxAPIC in normal operation.
Intel® 6700PXH 64-bit PCI Hub Datasheet
149
INTEL [ INTEL ]
