Register Description
3.8.2.2
Offset 00h: IDX—Index Register
Offset:
Default Value: 00h
00h
Attribute: RW
Size: 8 bits
The Index Register will select which indirect register appears in the window register to be
manipulated by software. Software will program this register to select the desired I/OxAPIC
internal register.
Bits
Type
Reset
Description
7:0
RW
0
Index (IDX): Indirect register to access.
3.8.2.3
Offset 10h: WND—Window Register
Offset:
Default Value: 00000000h
10–13h
Attribute: RW
Size: 32 bits
This is a 32-bit register specifying the data to be read or written to the register pointed to by the
Register Select register. This register can be accessed in byte quantities.
Bits
Type
Reset
Description
31:0
RW
0
Window (WND): Data to be written to the indirect register on writes, and
location of register data from the indirect register on reads.
3.8.2.4
Offset 20h: PAR—IRQ Pin Assertion Register
Offset:
Default Value: 000000xxh
20h
Attribute: RW, RO
Size: 32 bits
The IRQ Pin Assertion Register is present to provide a mechanism to scale the number of interrupt
inputs into the I/Ox APIC without increasing the number of dedicated input pins. When a device
that supports this interrupt assertion protocol requires interrupt service, that device will issue a
write to this register. Bits [4:0] written to this register contain the IRQ number for this interrupt.
The only valid values are 0–23.
Bits
Type
Reset
Description
31:5
4:0
RO
0
Reserved.
RW
xx
Assertion (PAR): Virtual pin to be asserted (active high). Writes to this
register are treated with edge triggered semantics regardless of what is
programmed in the RDL DWord, though the interrupt message is generated
directly from the contents of the RDL and RDH DWords.
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Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
