Register Description
3.8.1.21
Offset 4Eh: DSTS—Device Status Register (D0: F1, F3)
Offset:
Default Value: 0000h
4E-4Fh
Attribute: RWC, RO
Size: 16 bits
This register provides information on specific parameters of a PCI Express* device, in this case the
Intel® 6700PXH 64-bit PCI Hub.
Bits
Type
Reset
Description
15:6
5
RO
RO
0
0
Reserved.
Transactions Pending (TP): Not relevant for I/OxAPIC, since it does not
generate non-posted requests.
4
3
RO
0
0
Aux Power Detected (AUXPD): Intel® 6700PXH 64-bit PCI Hub does not
support aux power and hence this bit is reserved for the Intel® 6700PXH
64-bit PCI Hub.
RWC
Unsupported Request Detected (URD): This bit indicates that the Intel®
6700PXH 64-bit PCI Hub received an Unsupported request. The I/OxAPIC will
set this bit whenever it receives a configuration or memory write with bad
parity. It is also set on link unsupported request errors that are not specific to
any function within the Intel® 6700PXH 64-bit PCI Hub.
2
1
RWC
RWC
0
0
Fatal Error Detected (FED): The I/OxAPIC does not set this bit on its own,
but rather it is set on link fatal errors.
Non-Fatal Error Detected (NFED): The I/OxAPIC sets this bit whenever it
detects a write to I/OxAPIC (configuration or memory space) with bad data
parity. This bit is also set on link uncorrectable errors that are not specific to
any functions within the Intel® 6700PXH 64-bit PCI Hub.
0
RWC
0
Correctable Error Detected (CED): The I/OxAPIC does not set this bit on its
own, but rather it is set on link correctable errors.
Intel® 6700PXH 64-bit PCI Hub Datasheet
147
INTEL [ INTEL ]
