Register Description
3.8.1.20
Offset 4Ch: DEVCNTL—Device Control Register
(D0: F1, F3)
Offset:
Default Value: 0020h
4C – 4Dh
Attribute: RW; RO
Size: 16 bits
This register controls PCI Express* device specific (Intel® 6700PXH 64-bit PCI Hub) parameters.
Bits
Type
Reset
Description
15
14:12
11
RO
RO
R0
0
0
0
Reserved.
Max_Read_Request_Size (MRRS): Does not apply to the I/OxAPIC.
Enable No Snoop (ENS): This does not apply to the Intel® 6700PXH 64-bit
PCI Hub since it does not set the NS bit on MSI Transactions it generates.
10
9
R0
RO
RO
RW
0
0
Auxiliary (AUX) Power PM Enable (AUXPPME): The Intel® 6700PXH 64-bit
PCI Hub ignores this bit since it does not support auxiliary power.
Phantom Function Enable (PFE): The Intel® 6700PXH 64-bit PCI Hub
ignores this bit since it does not support phantom functions.
8
0
Extended Tag Field Enable (ETFE): The Intel® 6700PXH 64-bit PCI Hub
ignores this bit since it supports only 5-bit tag.
7:5
001b
Max_ Payload_Size (MPS): Does not affect the I/OxAPIC since it does not do
writes greater than a DWORD.
4
3
RO
0
0
Enable Relaxed Ordering (ERO): Not applicable or used by the I/OxAPIC.
RW
Unsupported Request Reporting Enable (URRE): This bit enables reporting
of Unsupported Requests when set to a 1. It is used by the I/OxAPIC to enable
reporting of ERR_FATAL or ERR_NONFATAL messages on the PCI Express*
interface for reporting Unsupported Requests errors, such as data parity errors
on writes to the I/OxAPIC (configuration or memory space).
Refer to Section 6.2 of the PCI Express* Base Specification, Revision 1.0a for
further details.
2
1
RW
RW
0
0
Report Fatal Errors: Used to gate the generation of ERR_FATAL message on
Fatal link errors. Refer to the PCI Express* Base Specification, Revision 1.0a
for information on how this bit is used to report fatal errors in the context of
multi-function devices like the Intel® 6700PXH 64-bit PCI Hub. This bit is not
used by the APIC per se.
Non-Fatal Error Reporting Enable (NFERE): This bit controls reporting of
non-fatal errors. Used by I/OxAPIC to gate the generation of the
ERR_NONFATAL message on data parity errors to it.
0 = Disable.
1 = Intel® 6700PXH 64-bit PCI Hub will report non-fatal errors.
Refer to Section 6.2 of the PCI Express* Base Specification, Revision 1.0a for
further details.
0
RW
0
Correctable Error Reporting Enable (CERE): This bit controls reporting of
correctable errors. When set to “1”, the Intel® 6700PXH 64-bit PCI Hub is
enabled to generate ERR_CORR message on the PCI Express* bus. Not used
by I/OxAPIC in normal operation.
0 = Disable.
1 = Intel® 6700PXH 64-bit PCI Hub will report correctable errors.
146
Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
