Register Description
3.8.1.19
Offset 48h: EXP_DCAP—PCI Express* Device Capability
Register (D0: F1, F3)
Offset:
Default Value: 00000001h
48 – 4Bh
Attribute: RO
Size: 32 bits
This register identifies PCI Express* device specific capabilities.
Bits
Type
Reset
Description
31:28
27:26
RO
RO
0
0
Reserved.
Captured Slot Power Limit Scale (CSPLS): Specifies the scale used for the
Slot Power Limit Value.
Range of Values:
00b = 1.0x
01b = 0.1x
10b = 0.01x
11b = 0.001x
This value is set by the Set_Slot_Power_Limit message.
In combination with the Slot Power Limit value, specifies the upper limit on
power supplied by slot. Power limit (in Watts) calculated by multiplying the
value in this field by the value in the Slot Power Limit Value field.
25:18
RO
0
Captured Slot Power Limit Value (CSPLV): In combination with the Slot
Power Limit Scale value, specifies the upper limit on power supplied by slot.
Power limit (in Watts) calculated by multiplying the value in this field by the
value in the Slot Power Limit Scale field. This value is set by the
Set_Slot_Power_Limit message.
17:12
11:9
RO
RO
0
0
Reserved.
Endpoint L1s Acceptable Latency (EL1AL): The Intel® 6700PXH 64-bit PCI
Hub does not support L1 Link State Power Management (LSPM).
8:6
5
RO
RO
RO
RO
0
0
Endpoint L0s Acceptable Latency (EL0AL): The Intel® 6700PXH 64-bit PCI
Hub wants the least latency possible out of L0s
Extended Tag Field Supported (ETFS): The Intel® 6700PXH 64-bit PCI Hub
supports only a 5-bit tag.
4:3
2:0
0
Phantom Functions Supported (PFS): The Intel® 6700PXH 64-bit PCI Hub
does not support phantom functions.
001b
Max_ Payload_Size Supported (MPSS): This field is set to a value of 001b,
signifying that the Intel® 6700PXH 64-bit PCI Hub supports a maximum
payload size of 256 byte packets.
Intel® 6700PXH 64-bit PCI Hub Datasheet
145
INTEL [ INTEL ]
