Register Description
3.8.1.9
Offset 0Dh: MLAT—Master Latency Timer Register
(D0: F1, F3)
Offset:
Default Value: 00h
0Dh
Attribute: RO
Size: 8 bits
This Master Latency Timer register does not apply to PCI Express*, and thus it is hardwired to zero
by the Intel® 6700PXH 64-bit PCI Hub.
Bits
Type
Reset
Description
7:0
RO
0
Latency Timer (LAT): Reserved.
3.8.1.10
Offset 0Eh: HDRTYPE—Header Type Register (D0: F1, F3)
Offset:
Default Value: 00h
0Eh
Attribute: RO
Size: 8 bits
Bits
Type
Reset
Description
7:0
RO
0
Header Type (HDRTYPE): This indicates that it is a type "00" header (normal
PCI device) and that it is part of a multi-function device.
3.8.1.11
3.8.1.12
Offset 0Fh: BIST—Built-in Self-Test Register (D0: F1, F3)
Offset:
Default Value: 00h
0Fh
Attribute: RO
Size: 8 bits
Bits
Type
Reset
Description
Built-In Self-Test (BIST): Reserved.
7:0
RO
0
Offset 10h: MBAR—Memory Base Register (D0: F1, F3)
Offset:
Default Value: 00000000h
10–13h
Attribute: RW, RO
Size: 32 bits
This register contains the I/OxAPIC Base Address for the I/OxAPIC memory space.
Bits
Type
Reset
Description
31:12
11:4
3
RW
RO
RO
RO
0
0
0
0
Address (ADDR): These bits determine the base address of the I/OxAPIC.
Reserved.
Prefetchable (PF): A value of 0 indicates that the BAR is not prefetchable.
2:1
Location (LOC): '00' indicates that the address can be located anywhere in
the 32-bit address space.
0
RO
0
Space Indicator (SI): Indicates that the BAR is in memory space.
142
Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
