Register Description
3.8.1.6
Offset 08h: REVID—Revision ID Register (D0: F1, F3)
Offset:
Default Value: 00h
08h
Attribute: RO
Size: 8 bits
Identifies the I/OxAPIC stepping of the Intel® 6700PXH 64-bit PCI Hub.
Bits
Type
Reset
Description
7:0
RO
0
Revision ID (RID): Indicates the step of the I/OxAPIC of the Intel® 6700PXH
64-bit PCI Hub.
00h = A0 stepping.
04h = B0 stepping.
08h = C0 stepping.
3.8.1.7
Offset 09h: CC—Class Code Register (D0: F1, F3)
Offset:
Default Value: 080020h
09–0Bh
Attribute: RO
Size: 24 bits
This register contains the base class, sub-class and programming interface codes.
Bits
Type
Reset
Description
23:16
RO
08h
Base Class Code (BCC): The value of '08h' indicates that this is a generic
system peripheral.
15:8
7:0
RO
RO
0
Sub Class Code (SCC): The value of '00h' indicates that this generic
peripheral is an interrupt controller.
20h
Programming Interface (PIF): The value of '20h' indicates that this interrupt
peripheral is an I/OxAPIC.
3.8.1.8
Offset 0Ch: CLS—Cache Line Size Register (D0: F1, F3)
Offset:
Default Value: 00h
0Ch
Attribute: RO
Size: 8 bits
This register is set by the system BIOS and the OS to equal the system cache line size. However,
note that legacy PCI 2.3 software may not always be able to program this field directly, especially
in the case of hot plug devices. This field is implemented by PCI Express* devices as a read/write
field for legacy compatibility purposes but has no impact on any PCI Express* device
functionality.
Bits
Type
Reset
Description
7:0
RO
0
Cache Line Size (CLS): Reserved.
Intel® 6700PXH 64-bit PCI Hub Datasheet
141
INTEL [ INTEL ]
