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6700PXH 参数 Datasheet PDF下载

6700PXH图片预览
型号: 6700PXH
PDF下载: 下载PDF文件 查看货源
内容描述: 64位PCI中枢 [64-bit PCI Hub]
分类和应用: PC
文件页数/大小: 194 页 / 2283 K
品牌: INTEL [ INTEL ]
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Register Description  
Bits  
Type  
Reset  
Description  
27  
RW  
1
MRL Sensor Interrupt Mask (MSIM): If this bit is set, system interrupts from  
MRL Sensor Change Detected are masked. The state of this bit has no effect  
on the state of the MRL Sensor Change Detected bit.  
26  
25  
24  
RW  
RW  
RW  
1
1
1
Attention Button Interrupt Mask (ABIM): If this bit is set, system interrupts  
from Attention Button Press Detected are masked. The state of this bit has no  
effect on the state of the Attention Button Press Detected bit.  
Isolated Power Fault Interrupt Mask (IPFIM): If this bit is set, system  
interrupts from Isolated Power Fault Detected are masked. The state of this  
bit has no effect on the state of the Isolated Power Fault Detected bit.  
Card Presence Interrupt Mask (CPIM): If this bit is set, system interrupts  
from Card Presence Change Detected are masked. The state of this bit has  
no effect on the state of the Card Presence Change Detected bit.  
3.8  
I/OxAPIC Interrupt Controller Registers  
(Function 1 and 3)  
The Intel® 6700PXH 64-bit PCI Hub contains two I/OxAPIC controllers, both of which reside on  
the primary bus. The intended use of these controllers for the Intel® 6700PXH 64-bit PCI Hub is to  
have the interrupts from PCI bus A connected to the interrupt controller on Function 1, and have  
the interrupts on PCI bus B connected to the interrupt controller on Function 3. The Intel®  
6702PXH 64-bit PCI Hub supports a single I/OxAPIC controller, corresponding to Function 1.  
3.8.1  
PCI Configuration Space Registers  
3.8.1.1  
Register Summary  
Note: Registers that are not shown should be considered Reserved.  
Address  
Offset  
Symbol  
Register Name  
Default  
Attribute  
00–01h  
02–03h  
VID  
DID  
Vendor ID Register  
Device ID Register  
8086h  
RO  
RO  
0326h (F0)  
0327h (F3)  
04–05h  
06–07h  
08h  
CMD  
STS  
Command Register  
0000h  
0010h  
00h  
RO  
RWO, RO  
RO  
Status Register  
REVID  
CC  
Revision ID Register  
Class Code Register  
Cache Line Size Register  
Master Latency Register  
Header Type Register  
Built-in Self Test Register  
Memory Base Register  
Subsystem Identifier Register  
09–0Bh  
0Ch  
080020h  
00h  
RO  
CLS  
RO  
0Dh  
MLAT  
HEADTYP  
BIST  
00h  
RO  
0Eh  
00h  
RO  
0Fh  
00h  
RO  
10–13h  
2C–2Fh  
MBAR  
SSID  
00000000h  
00000000h  
RW, RO  
RWOS  
Intel® 6700PXH 64-bit PCI Hub Datasheet  
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