Register Description
Bits
Type
Reset
Description
15:8
RO
78h or
D8h
Next Capability Pointer (NCPTR): Points to the next capability item. Default
is 78h when SHPC is enabled (HPx_SLOT[3] = 1), and D8h when SHPC is
disabled (HPx_SLOT[3] = 0).
7:0
RO
01h
Capability ID (CAPID): Capability ID indicates PCI compatible Power
Management.
3.5.1.49
Offset 70h: EXP_PMSTSCNTL – PCI Express* Power
Management Status and Control Register (D0:F0, F2)
Offset:
Default Value: xx000000h
70– 73h
Attribute: RWCS, RWS, RW, RO
Size: 32 bits
Bits
Type
Reset
Description
31:24
RO
0
Data (DAT): The Intel® 6700PXH 64-bit PCI Hub does not support this data
register.
23:16
15
RO
0
0
Reserved.
RWCS
PME Status (PMEST): This bit is set when the Intel® 6700PXH 64-bit PCI
Hub would have normally sent a PME request on behalf of SHPC,
independent of the state of the PME_En bit. The SHPC requests a PME
message when the Intel® 6700PXH 64-bit PCI Hub is in the D3hot state and a
hot plug operation is requested. Refer to the SHPC specification for the details
of PME generation.
14:13
RO
0
Data Scale (DATS): The Intel® 6700PXH 64-bit PCI Hub does not implement
the Data register and hence these two bits are “0.”
12:9
8
RO
0
0
Data Select (DATSEL): Reserved since the Data register is not implemented.
RWS
PME Enable (PME_EN): Gates assertion of the PME message on behalf of
the SHPC.
7:2
1:0
RO
0
Reserved.
RW
00b
Power State (PWR_ST): This 2-bit field is used both to determine the current
power state of a function and to set the function into a new power state. The
Intel® 6700PXH 64-bit PCI Hub supported field values are given below:
00b – D0
01b – Reserved
10b – Reserved
11b – D3hot
If software attempts to write an unsupported reserved state to this field, the
write operation must complete normally on the bus; however, the data is
discarded and no state change occurs.
108
Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
