Register Description
3.5.1.46
Offset 64h: MSI_MUA—PCI Express* MSI Message Upper
Address Register (D0:F0, F2)
Offset:
Default Value: 00000000h
64 – 67h
Attribute: RW, RO
Size: 32 bits
Bits
Type
Reset
Description
31:2
RW
0
Message Address (MESADDR): Upper 32 bits of the system specified
message address, always DWord aligned.
1:0
RO
0
Reserved.
3.5.1.47
Offset 68h: MSI_MD—PCI Express* MSI Message Data
Register (D0:F0, F2)
Offset:
Default Value: 0000h
68 – 69h
Attribute: RW
Size: 16 bits
Bits
Type
Reset
Description
15:0
RW
0
Data (DATA): This 16-bit field is programmed by system software if MSI is
enabled. Its content is driven onto the lower word (D[15:0]) of the MSI memory
write transaction.
3.5.1.48
Offset 6Ch: EXP_CAPSTR – PCI Express* Power
Management Capability Structure Register (D0:F0, F2)
Offset:
Default Value: 000002xxh
6C – 6Fh
Attribute:RO
Size: 32 bits
This register identifies specific PCI Express* Power Management capabilities.
Bits
Type
Reset
Description
31:27
RO
19h
PME_Support (PMES): The Intel® 6700PXH 64-bit PCI Hub supports PME
assertion on behalf of the SHPC when in the D3hot state. The Intel®
6700PXH 64-bit PCI Hub does not generate PME from the D3cold state.
26
25
RO
RO
RO
RO
0
0
0
0
D2 Support (D2S): The Intel® 6700PXH 64-bit PCI Hub does not support the
D2 device state.
D1 Support (D1S): The Intel® 6700PXH 64-bit PCI Hub does not support the
D1 device state.
24:22
21
Aux Current (AUXC): The Intel® 6700PXH 64-bit PCI Hub does not support
Aux power.
Device Specific Initialization (DSI): The Intel® 6700PXH 64-bit PCI Hub
does not require device specific initialization when transitioned to D0 from
D3hot state, so this bit is zero.
20
19
RO
RO
0
0
Reserved.
PME Clock (PMECLK): This is not applicable to PCI Express* and hence
hardwired to 0.
18:16
RO
02h
Version (VERS): The Intel® 6700PXH 64-bit PCI Hub PM Implementation is
compliant with the PCI Power Management Interface Specification Revision
1.1.
Intel® 6700PXH 64-bit PCI Hub Datasheet
107
INTEL [ INTEL ]
