Register Description
3.5.1.39
Offset 50h: EXP_LCAP—PCI Express* Link Capabilities Register
(D0:F0, F2)
Offset:
Default Value: 000B0211h
50 – 53h
Attribute:RO
Size: 32 bits
This register identifies PCI Express* Link specific capabilities.
Bits
Type
Reset
Description
31:18
17:15
RO
RO
0
Reserved.
111b
L1 Exit Latency (L1EL): L1 transition is not supported by the Intel® 6700PXH
64-bit PCI Hub.
14:12
RO
110b
L0s Exit Latency (L0EL): The value in these bits is influenced by bit 6 in the
link control register. Note that software could write the bit 6 in link control
register to either a 1 or 0 and these bits should change accordingly. The
mapping is shown below:
Bit 6 PCI Express* Link Control Link Capabilities Bits 14:12
0
1
110b = 2-4 us
010b = 128 ms to less than 256 ms
11:10
9:4
RO
RO
RO
1h
08h
1h
Active State Link PM Support (ASLPMS): Intel® 6700PXH 64-bit PCI Hub
only supports Active State L0s.
Maximum Link Width (MLW): The Intel® 6700PXH 64-bit PCI Hub supports
a X8 link maximum.
3:0
Maximum Link Speed (MLS): The Intel® 6700PXH 64-bit PCI Hub supports
2.5 Gbps.
3.5.1.40
Offset 54h: EXP_LCNTL – PCI Express* Link Control Register
(D0:F0, F2)
Offset:
Default Value: 0000h
54 – 55h
Attribute:RW, RO
Size: 16 bits
This register controls PCI Express* Link specific parameters.
Bits
Type
Reset
Description
15:8
7
RO
0
0
Reserved.
RW
Extended Synch (EXTS): This bit when set forces extended transmission of
4096 fast training sequence (FTS) ordered sets in FTS and an extra 1024
training sequence one (TS1) at exit from L1 prior to entering L0. This mode
provides external devices monitoring the link time to achieve bit and symbol
lock before the link enters L0 state and resumes communication. Default
value for this bit is 0.
6
RW
RO
0
0
Common Clock Configuration (CCC): This bit when set indicates that Intel®
6700PXH 64-bit PCI Hub and the component at the opposite end of this Link
are operating with a distributed common reference clock. A value of 0
indicates that this component and the component at the opposite end of this
Link are operating with asynchronous reference clock. Note that this bit is
used to reflect the proper L0s exit latency value in the EXP_LSTS register.
Components utilize this common clock configuration information.
5:2
Reserved.
104
Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
