Register Description
3.5.1.43
Offset 5Dh: MSI_NXTPTR—PCI Express* MSI Next Pointer
Register (D0:F0, F2)
Offset:
Default Value: 6Ch
5Dh
Attribute: RO
Size: 8 bits
Bits
Type
Reset
Description
7:0
RO
6Ch
Next Pointer (NXT_PTR): Pointer to the next item in the capabilities list. Must
be NULL for the final item in the list.
3.5.1.44
Offset 5Eh: MSI_MCNTL—PCI Express* MSI Message Control
Register (D0:F0, F2)
Offset:
Default Value: 0080h
5E – 5Fh
Attribute: RW; RO
Size: 16 bits
Bits
Type
Reset
Description
15:8
7
RO
RO
0
1
Reserved.
64Bit Address Capable (64CAP): The Intel® 6700PXH 64-bit PCI Hub is
capable of generating a 64-bit message address.
6:4
RW
0
Multiple Message Enable (MMEN): These bits are RW for software
compatibility, but only one message is ever sent by the Intel® 6700PXH 64-bit
PCI Hub.
3:1
0
RO
0
0
Multiple Message Capable (MMCAP): Intel® 6700PXH 64-bit PCI Hub
supports only one message.
RW
MSI Enable (MSIEN): If set to a 1, the Intel® 6700PXH 64-bit PCI Hub is
permitted to use MSI to request service and is prohibited from using its INTx#
pin. Thus MSI would be enabled and SHPC would not use the IRQ[23]# wired
to the internal I/OxAPIC to generate interrupts.
If set to a 0, the Intel® 6700PXH 64-bit PCI Hub is prohibited from using MSI
to request service.
3.5.1.45
Offset 60h: MSI_MA—PCI Express* MSI Message Address
Register (D0:F0, F2)
Offset:
Default Value: 00000000h
60 – 63h
Attribute: RW, RO
Size: 32 bits
Bits
Type
Reset
Description
31:2
RW
0
Message Address (MESADDR): Lower 32 bits of the system specified
message address, always DWord aligned.
1:0
RO
0
Reserved.
106
Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
