Register Description
Bits
Type
Reset
Description
1:0
RW
0
Active State Link PM Control (ASLPMC): Enables Intel® 6700PXH 64-bit
PCI Hub to enter L0s, not used by I/OxAPIC in normal operation.
00 L0s entry disabled
01 Intel® 6700PXH 64-bit PCI Hub enters L0s per the specification
requirements for L0s entry.
10 L0s entry disabled
11 Intel® 6700PXH 64-bit PCI Hub enters L0s per the specification
requirements for L0s entry.
3.5.1.41
Offset 56h: EXP_LSTS – PCI Express* Link Status Register
(D0:F0, F2)
Offset:
56 – 57h
Attribute:RO
Size: 16 bits
Default Value: 0001h (X1 link)
0041h (x4 link)
0081h (X8 link)
This register provides information about PCI Express* Link specific parameters.
Bits
Type
Reset
Description
15:10
9:4
RO
RO
0
Reserved.
0h (X1) Negotiated Link Width (NLW): This field indicates the negotiated width of
4h (X4) PCI Express* Link. Defined encodings are:
8h (X8)
000000b X1
000100b X4
001000b X8
3:0
RO
0001b
Link Speed (LS): This field indicates the negotiated Link speed of the PCI
Express* Link. The Intel® 6700PXH 64-bit PCI Hub supports only 2.5 Gbps.
3.5.1.42
Offset 5Ch: MSI_CAPID— PCI Express* MSI Capability Identifier
Register (D0:F0, F2)
Offset:
Default Value: 05h
5Ch
Attribute: RO
Size: 8 bits
This register identifies whether the function is MSI capable.
Bits
Type
Reset
Description
7:0
RO
05h
Capability ID (CAP_ID): The value of 05h in this field identifies the function as
Message Signaled Interrupt capable.
Intel® 6700PXH 64-bit PCI Hub Datasheet
105
INTEL [ INTEL ]
