Registers
14.8
Bring-up and Debug Registers (Function 6)
14.8.1
SPAD[1:0]: Scratch Pad
These bits have no effect upon the operation of the AMB. They are intended to be used
by software for tracking changes in AMB state. These two registers are in different
functions.
Device:
NodeID
Function: 7, 6
Offset:
7Ch
Bit
Attr
Default
Description
31:0
RW
0000_0000h FREE:
These bits are available for software definition.
®
14.8.2
Southbound FBD Intel Interconnect BIST Registers
®
14.8.2.1
SBFIBPORTCTL: Southbound FBD Intel Interconnect BIST Port
Control Register
This register controls the operation of the Intel® Interconnect BIST (Intel® IBIST)
logic. Please refer to Fully-Buffered DIMM DFx Specification for detailed description of
the operation of Intel IBIST.
Device:
NodeID
Function: 6
Offset:
Bit
80h
Attr
Default
Description
31:24
23
RV
00h
0
Reserved
RWST
SBNBMAP: Loopback mapping bit
This bit will be sent during TS1 to the slave to specify which lanes needs to be
looped back. Actual lanes looped back is specified in the FBD Architecture Spec.
22
RWST
0
CMMSTR: Compliance Measurement Mode start
This puts the Intel IBIST logic in CMM mode and Intel IBIST TX engine will start
transmitting Intel IBIST patterns.
21:12
11:8
RWCST
ROST
000h
0h
ERRCNT: Error Counter
Total number of frames with errors that were encountered by this port.
ERRLNNUM: Error Lane Number
This points to the first lane that encountered an error. If more than one lane
reports an error in a cycle, the most significant lane number that reported the
error will be logged.
7:6
RWCST
00
ERRSTAT: Port Error Status
When Intel IBIST is started, status goes to 01 until first start delimiter is
received and then goes to 00 until the end or to10 if an error occurs.
00: No error.
01: Did not receive first start delimiter.
10: Transmission error (first error).
11: Reserved for future use
5
RWST
0
AUTOINVSWPEN: Auto Inversion sweep enable
This bit enables the inversion shift register to continuously rotate the pattern in
the FIBTXSHFT and FIBRXSHFT registers.
0: Disable Auto-inversion
1: Enable Auto-inversions
Intel® 6400/6402 Advanced Memory Buffer Datasheet
231
INTEL [ INTEL ]
