Registers
Device:
NodeID
Function: 5
Offset:
F0h
Bit
Attr
Default
Description
15:12
RWCST
0h
EV: Event Bus EV[3:0]
set on event and cleared by writing
11:9
8:1
RWCST
RWST
0h
0h
MMEVENT: MMEVENT[2:0] selected by MMEVENTSEL
set on event and cleared by writing
LINKST: FBD Link State: Disable[1], calibrate[2], training[3],
testing[4], pollling[5], config[6], l0[7], L0s or recalibrate[8]
One hot encoding of FBD link state
0
RO
0
NULL: Null Event: Bit never set
14.7.3
Error Injection Registers
14.7.3.1
EICNTL: Error Injection Control
This register controls the AMB error injection logic.
Device:
NodeID
Function: 5
Offset:
FCh
Bit
Attr
Default
Description
EIEN:Error Injection Enable
7
RW
0
1= Error Injection enabled
0= Error Injection disabled
6:4
RW
000
EITYPE: Type of error injection
111 = Reserved;
110 = Reserved
101 = Force NB Error bit on next Status return
100 = Force Alert on event
011 = Reserved
010 =Reserved
001= Corrupt NB CRC on event
000= No error injection
3:0
RV
0h
Reserved
14.7.3.2
STUCKL: Stuck “ON” FBD Lanes
This register selects FBD Lanes to be stuck at “Electrical Idle” following a write to this
register.
Device:
NodeID
Function: 5
Offset:
Bit
FEh
Attr
Default
Description
7:4
3:0
RV
0h
Fh
Reserved
NBSTUCK: NB Lane to be driven to EI to simulate a failed lane
RWST
•
0h = lane 0: Dh = lane 13 and > 13 = NOP
230
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
