Registers
Device:
NodeID
Function: 5
Offset:
Bit
E8h
Attr
Default
Description
29:25
24:20
RV
00h
04h
Reserved
RWST
LAITRIGGER10:
Local event selected and transmitted to LAI as TRIGGER10
Default on power on to SB Unit Testing State detect
19:15
14:10
9:5
RWST
RWST
RWST
RWST
1Ah
0Dh
0Ch
09h
LAITRIGGER9:
Local event selected and transmitted to LAI as TRIGGER9
Default on power on to SB CRC error detect
LAITRIGGER8:
Local event selected and transmitted to LAI as TRIGGER8
Default on power on to Event Bus[1] event
LAITRIGGER7:
Local event selected and transmitted to LAI as TRIGGER7
Default on power on to Event Bus[0] event
4:0
LAITRIGGER6:
Local event selected and transmitted to LAI as TRIGGER6
Default on power on to MM[0] event= Write Register in
command slot B
14.7.2.14 EVENT: Local LAI Event Register
This register sets a bit if a local event is hit. Except for QUALFLAG, most local event
signal internal to the AMB may assert for only one cycle. The event bits in this register
remain set once asserted so that the history of the event being set is not lost.
Note: The 5-bit select fields in the EVENTSEL0, EVENTSEL1, EVENTSEL2 and EVBUS
registers use the bit mapping of this register to identify which local event to select.
• For example, if EVENTSEL1.laitrigger0[4:0] = 26 decimal then trigger0 is
connected to the SB CRC error event.
• For example, if EVENTSEL1.laitrigger0[4:0] = 12 decimal then trigger0 is
connected to the inbound EVBus[0] event, and so forth.
Device:
NodeID
Function: 5
Offset:
Bit
F0h
Attr
Default
Description
31
RWCST
RWCST
0
Spare:
30:25
00h
ERROR EVENTS:
•
SB/NB failover[25],
when unmasked:
•
•
•
•
•
SB CRC error[26],
thermal overload[27],
clock training violation (< 6 transitions in 512 UI) [28],
unimplemented register access[29],
other implementation specific errors[30]
set on event and cleared by writing
24
RWCST
RWCST
0
QUALFLAG:
23:16
00h
INBANDEV: SB link in-band EV[7:0]
set on event and cleared by writing
Intel® 6400/6402 Advanced Memory Buffer Datasheet
229
INTEL [ INTEL ]
