Registers
14.7.2.8
SBMASKL1: Lower Southbound Mask Register 1
This register sets the lower 32 bits of data mask for match southbound command 1.
Device:
NodeID
Function: 5
Offset:
D4h
Bit
31:0
Attr
RWST
Default
00100000h
Description
CMDMASK:
Lower 32bits [31:0] of southbound command mask.
0: Do not include this bit in match comparison
1: Include this bit in match comparison
power on default = match Activate
14.7.2.9
SBMASKL2: Lower Southbound Mask Register 2
This register sets the lower 32 bits of data mask for match southbound command 2.
Device:
NodeID
Function: 5
Offset:
D8h
Bit
31:0
Attr
RWST
Default
001FC000h
Description
CMDMASK:
Lower 32bits [31:0] of southbound command mask.
0: Do not include this bit in match comparison
1: Include this bit in match comparison
power on default = match Write Config Reg
14.7.2.10
MMEVENTSEL: Match/Mask Event Selection Register
Selects 1 of 13 local match events described below for promotion to local event select.
Three local events MMEVENT[2:0] can be associated with one of these local match
events.
Device:
NodeID
Function: 5
Offset:
DCh
Bit
15:12
11:8
7:4
3:0
Attr
RV
RWST
RWST
RWST
Default
0h
2h
Ah
3h
Reserved
MMEVENT2SEL:
default: match pattern 0 to slot A only for sync
MMEVENT1SEL:
default: match pattern 1 to slot A, B, or C for activate
MMEVENT0SEL:
default: match pattern 2 to slot B only for write config reg
Description
.
MM
Event
15:13
12
Reserved
Description
FRAMEMATCH
Bit pattern in slot A matches SBMATCH/SBMASK 0
AND
Bit pattern in slot B matches SBMATCH/SBMASK 1
AND
Bit pattern in slot C matches SBMATCH/SBMASK 2
226
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL CORPORATION ]
