Registers
14.7.2.8
SBMASKL1: Lower Southbound Mask Register 1
This register sets the lower 32 bits of data mask for match southbound command 1.
Device:
NodeID
Function: 5
Offset:
Bit
D4h
Attr
Default
Description
31:0 RWST
00100000h
CMDMASK:
Lower 32bits [31:0] of southbound command mask.
0: Do not include this bit in match comparison
1: Include this bit in match comparison
power on default = match Activate
14.7.2.9
SBMASKL2: Lower Southbound Mask Register 2
This register sets the lower 32 bits of data mask for match southbound command 2.
Device:
NodeID
Function: 5
Offset:
D8h
Bit
Attr
Default
Description
31:0
RWST
001FC000h
CMDMASK:
Lower 32bits [31:0] of southbound command mask.
0: Do not include this bit in match comparison
1: Include this bit in match comparison
power on default = match Write Config Reg
14.7.2.10 MMEVENTSEL: Match/Mask Event Selection Register
Selects 1 of 13 local match events described below for promotion to local event select.
Three local events MMEVENT[2:0] can be associated with one of these local match
events.
Device:
NodeID
Function: 5
Offset:
Bit
DCh
Attr
Default
Description
15:12
11:8
RV
0h
2h
Reserved
RWST
MMEVENT2SEL:
default: match pattern 0 to slot A only for sync
7:4
3:0
RWST
RWST
Ah
3h
MMEVENT1SEL:
default: match pattern 1 to slot A, B, or C for activate
MMEVENT0SEL:
default: match pattern 2 to slot B only for write config reg
.
MM
Event
Description
15:13
12
Reserved
FRAMEMATCH
Bit pattern in slot A matches SBMATCH/SBMASK 0 AND
Bit pattern in slot B matches SBMATCH/SBMASK 1 AND
Bit pattern in slot C matches SBMATCH/SBMASK 2
226
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
