Registers
14.7
DFX Registers (Function 5)
14.7.1
Transparent Mode Registers
14.7.1.1
TRANSCFG: Transparent Mode Configuration
This register enables and controls FBD DFX transparent mode features.
.
Device:
NodeID
Function: 5
Offset:
Bit
3Ch
Attr
Default
Description
31:29
28
RV
0h
0
Reserved
RWST
ENDOUT: enable data output on transparent data/status pins when
set, output status when clear
27
RWST
0
LGFBITS: log bits that fail the compare when set, log raw read data
when clear.
26
RWST
RWST
0
LGFFAIL: log first failure in any burst position.
25:24
00
BSTPOS: burst position to log data/failed bits from when LGFFAIL bit
is not set.
0 = first burst in bl4 or bl8 mode
1 = last burst of bl4, second burst of bl8
2 = third burst of bl8
3 = last burst of bl8
23:20
19:16
RWST
RWST
0h
0h
DRAMRD: byte of data bus selected to be output on transparent
data/status pins when ENDOUT bit is set.
8= DQS 17 and DQS 8
7= DQS 16 and DQS 7
...
0 = DQS 9 and DQS 0
DRAMWR: byte of data bus selected to receive transparent write
data, and byte of data bus to be compared against transparent read
data.
Fh = all bytes
8= DQS 17 and DQS 8
7= DQS 16 and DQS 7
...
0 = DQS 9 and DQS 0
15:0
RWST
0000h
DFTDATA: default data for bytes not selected by the DRAMWR field.
This field has early/even data in the upper 8 bits, and late/odd data
in the lower 8 bits.
14.7.1.2
TRANDERR[8:0]: Transparent Mode Data Error Logs
This register stores data returned from DRAM byte groups on failing transparent mode
tests.
Device:
NodeID
Function: 5
Offset:
Bit
50h, 4Eh, 4Ch, 4Ah, 48h,46h, 44h, 42h, 40h
Attr
Default
Description
15:8
7:0
RWST
RWST
00h
00h
LATE_DATA:
EARLY_DATA:
14.7.1.3
TRANSCTRL: Transparent Mode Control
222
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
