Registers
Device:
NodeID
Function: 5
Offset:
BCh
Bit
Attr
Default
Description
15:8
RWST
00h
CMD1:
Upper 8 bits [39:32] of southbound command 1
7:0
RWST
00h
CMD0:
Upper 8 bits [39:32] of southbound command 0
Match and Mask bit numbering of SB frames is as follows:
• where N= 0 for slot A, 4 for slot B and 8 for slot C
Table 14-17.Bit Locations for SB Match and Mask
Xfr\lane
0 + N
9
8
7
6
5
4
3
2
1
0
B36
B32
B28
B24
B20
B16
B12
B8
B9
B4
B5
B6
B7
B0
B37
B38
B39
B33
B34
B35
B29
B30
B31
B25
B26
B27
B21
B22
B23
B17
B18
B19
B13
B14
B15
B1
B2
B3
1 + N
B10
B11
2 + N
3 + N
14.7.2.3
SBMATCHL0: Lower Southbound Match Register 0
This register sets the lower 32 bits of data match for match southbound command 0.
Device:
NodeID
Function: 5
Offset:
C0h
Bit
Attr
Default
Description
31:0
RWST
00004000h
CMD:
Lower 32bits [31:0] of southbound command
power on default = match Synch
14.7.2.4
SBMATCHL1: Lower Southbound Match Register 1
This register sets the lower 32 bits of data match for match southbound command 1.
Device:
NodeID
Function: 5
Offset:
C4h
Bit
Attr
Default
Description
31:0
RWST
00100000h
CMD:
Lower 32bits [31:0] of southbound command
power on default = match Activate
224
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
