Registers
14.7.2.5
SBMATCHL2: Lower Southbound Match Register 2
This register sets the lower 32 bits of data match for match southbound command 2.
Device:
NodeID
Function: 5
Offset:
C8h
Bit
Attr
Default
Description
31:0
RWST
00014000h
CMD:
Lower 32bits [31:0] of southbound command
power on default = match Write Config Reg
14.7.2.6
SBMASKU: Upper Southbound Mask Register
This register sets the upper 8 bits of data mask for three southbound commands.
Device:
NodeID
Function: 5
Offset:
Bit
CCh
Attr
Default
Description
31:24
23:16
RV
00h
00h
Reserved
RWST
CMDMASK2:
Upper 8 bits [39:32] of southbound command 2 mask
0: Do not include this bit in match comparison
1: Include this bit in match comparison
15:8
7:0
RWST
RWST
00h
00h
CMDMASK1:
Upper 8 bits [39:32] of southbound command 1 mask
0: Do not include this bit in match comparison
1: Include this bit in match comparison
CMDMASK0:
Upper 8 bits [39:32] of southbound command 0 mask
0: Do not include this bit in match comparison
1: Include this bit in match comparison
14.7.2.7
SBMASKL0: Lower Southbound Mask Register 0
This register sets the lower 32 bits of data mask for match southbound command 0.
Device:
NodeID
Function: 5
Offset:
D0h
Bit
Attr
Default
Description
31:0
RWST
031FC000h
CMDMASK:
Lower 32bits [31:0] of southbound command mask.
0: Do not include this bit in match comparison
1: Include this bit in match comparison
power on default = match Sync
Intel® 6400/6402 Advanced Memory Buffer Datasheet
225
INTEL [ INTEL ]
