Registers
This register enables and controls FBD DFX transparent mode features.
Device:
NodeID
Function: 5
Offset:
80h
Bit
7:1
0
Attr
RV
RWST
Default
00h
0
Reserved
ENTRNSPMODE: Transparency Mode Enable
1 - Enables Transparency Mod
Description
14.7.2
14.7.2.1
Logic Analyzer Interface (LAI) Registers
LAI: LAI Operation Modes
This register controls and reports the AMB’s LAI mode and Qual controls.
Device:
NodeID
Function: 5
Offset:
B8h
Bit
31:16
15
Attr
RV
RWST
Default
0000h
0
Reserved
RAWMODE: data connected to LAI
0: LAI outputs contain initialization state information
prior to L0S then lane
data after L0S
1: LAI outputs connected to FBD data inputs even though valid timing is not
present
Reserved
QUALMODE:
Assert Qual for all non-filtered frames, or only assert Qual for all non-filtered
frames between start and stop events.
0: Ignore Qual start/stop events
1: Assert Qual after a start event, and deassert Qual after a stop events
FILTERSYNC:
Filter the frame (do not assert Qual) if the frame is a sync.
0: Disable sync filtering
1: Enable sync filtering
Reserved
QUALPERIOD:
Additional number of frames Qual remains asserted
Power-on default to 63
Description
14
13
RV
RWST
0
0
12
RWST
0
11:6
5:0
RV
RWST
00h
3Fh
14.7.2.2
SBMATCHU: Upper Southbound Match Register
This register sets the upper 8 bits of data match for three southbound commands.
Device:
NodeID
Function: 5
Offset:
BCh
Bit
31:24
23:16
Attr
RV
RWST
Default
00h
00h
Reserved
CMD2:
Upper 8 bits [39:32] of southbound command 2
Description
Intel® 6400/6402 Advanced Memory Buffer Datasheet
223
INTEL [ INTEL CORPORATION ]
