Registers
Device:
NodeID
Function: 4
Offset:
FCh
Bit
Attr
Default
Description
1:0
RWST
0h
R0ODTRD: ODT control during reads to CS0
14.6.2.5
DRAMDLLC: DDR I/O DLL Control
The formulas that show how the SLVLEN fields affect DQS delay timing are shown in
the DQSOFCS register definition section. The SLVLEN fields are set by hardware during
the DQS delay calibration. There are five SLVLEN fields, one for each “chunk”, or two
bytes, of the DDR I/O DQ pins. The SLVBYP bit can be toggled to reset the master DLL’s
in the DDR I/O.
Device:
NodeID
Function: 4
Offset:
Bit
C8h
Attr
Default
Description
23:22
21
RV
00h
0h
Reserved
RW
SLVBYP: DQS delay bypass
20:18
17:15
14:12
11:9
8:6
RWST
RWST
RWST
RWST
RWST
RV
3h
SLVLEN4: dqs17 & 8 coarse DQS delay
SLVLEN3: dqs16, 7, 15, & 6 coarse DQS delay
SLVLEN2: dqs14, 5, 13, & 4 coarse DQS delay
SLVLEN1: dqs12, 3, 11, & 2 coarse DQS delay
SLVLEN0: dqs10, 1, 9, & 0 coarse DQS delay
Reserved
3h
3h
3h
3h
5:0
00h
14.6.3
Firmware Support Registers
14.6.3.1
FIVESREG: Fixed 5’s Pattern
Constant value used for debug.
Device:
NodeID
Function: 4
Offset:
E8h
Bit
Attr
Default
Description
31:0
RO
55555555h FIVES: Hardwired to 5’s for read-return
14.6.3.2
AAAAREG: Fixed A’s Pattern
Constant value used for debug.
Device:
NodeID
Function: 4
Offset:
ECh
Bit
Attr
Default
Description
31:0
RO
AAAAAAAAh
AAAAS: Hardwired to A’s for read-return
Intel® 6400/6402 Advanced Memory Buffer Datasheet
221
INTEL [ INTEL ]
