Registers
Device:
NodeID
Function: 4
Offset:
Bit
F4h
Attr
Default
Description
DTIMR: disable time after read data
10:8
7:4
RWST
RWST
RWST
0h
0h
0h
ETIMW: enable time before write data
ETIMR: enable time before read data
3:0
14.6.2.3
DRAMISCTL: Miscellaneous DRAM DDR Cluster Control
Device:
NodeID
Function: 4
Offset:
Bit
F8h
Attr
Default
Description
31:13
12
RV
0000h Reserved
RWST
1
VOXSTART: Enable the voltage output crossing control loop in the DDR
I/O. This bit is AND’ed with the SPDPAR1011CUR.vox_start bit.
11
10
RW
RW
0
0
AVMODE: analog validation mode
OCDLOADENABLE: calibration load placed on incoming signals for DDR2
DRAM OCD calibration
9
8
RW
RW
0
0
OCDPOLSEL: set for pull up calibration, clear for pull down
OCDRCOMPEN:
7:0
RWST
11h
VREFSEL: vref selection
Details of DRAMISCTL VREF Field
Description
Settin
g
TBD
14.6.2.4
DDR2ODTC: DDR2 DRAM On-Die Termination Control
The DDR2ODTC controls the behavior of the ODT output (one ODT output per command
bus copy). There is a separate field to control the behavior for reads to rank0, reads to
rank1, writes to rank0, and writes to rank1. Only the lsb of each field is used, and the
msb has no effect. When an lsb of a field is set to one, the ODT pins will drive high, at
the appropriate time relative to data on the DDR bus, when the selected transaction
(read or write) is issued to the selected rank (0 or 1). If a field is set to 0, the ODT
output continues to drive low during the transaction, as it does during idle cycles.
Device:
NodeID
Function: 4
Offset:
FCh
Bit
Attr
Default
Description
7:6
RWST
0h
R1ODTWR: ODT control during writes to CS1
x1: ODT pins will drive high
x0: ODT pins remain driving low
5:4
3:2
RWST
RWST
0h
0h
R1ODTRD: ODT control during reads to CS1
R0ODTWR: ODT control during writes to CS0
220
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
