Registers
14.6.1.23 WPTRTC1: Write Pointer Timing Control 1
This register determines the DDR I/O FIFO write pointer fine delay timing for DQS17
and DQS8 signals when reading from rank 0 or rank 1.
Device:
NodeID
Function: 4
Offset:
Bit
D0h
Attr
Default
Description
7:4
3:0
RV
0h
0h
Reserved
DQS01708: Rank 0 DQS17 and DQS8 write pointer fine delay
RWST
14.6.1.24 DDQSCVDP and DDQSCADP
This set of 4 registers defines two 64 bit long data patterns used in the DQS Delay
Calibration. They are only used when DCALCSR.BASPAT is low. The 64 bit patterns
cover a data burst that is 32 DRAM clock cycles long. The DDQSCVDP registers define
the “victim” pattern, and the DDQSCADP defines the “aggressor” pattern. The victim
pattern is applied to one bit of each byte of the DDR data bus for 32 clock cycles, and
the aggressor pattern is applied to all other bits. The victim pattern is applied in turn to
each bit of each byte, creating a complete data pattern that is 8*32 data cycles long.
14.6.1.25 DDQSCVDP0: DQS DELAY CAL PATTERN 0
This register defines the last 32 bits of the 64 bit long “victim” data pattern.
Device:
NodeID
Function: 4
Offset:
D4h
Bit
Attr
Default
Description
31:0
RW
aaaa0a05h ENABLE:
14.6.1.26 DDQSCVDP1: DQS DELAY CAL PATTERN 1
This register defines the first 32 bits of the 64 bit long “victim” data pattern.
Device:
NodeID
Function: 4
Offset:
D8h
Bit
Attr
Default
Description
31:0
RW
5b339c5dh ENABLE:
14.6.1.27 DDQSCADP0: DQS DELAY CAL PATTERN 0
This register defines the last 32 bits of the 64 bit long “aggressor” data pattern.
Device:
NodeID
Function: 4
Offset:
DCh
Bit
Attr
Default
Description
31:0
RW
aaabffffh
ENABLE:
218
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
