Registers
14.6.1.20 DQSOFCS12: DQS Calibration Register
This register determines DQS17 & 8 fine DQS delay when reading from rank 1.
Device:
NodeID
Function: 4
Offset:
Bit
C7h
Attr
Default
Description
7:4
3:0
RWST
RWST
0h
0h
DQS17: Fine DLL delay
DQS08: Fine DLL delay
14.6.1.21 WPTRTC DDR I/O Write Pointer Timing
The two WPTRTC registers control the fine delay of the DDR I/O FIFO write pointers.
The formulas for delay shown in the DQSOFCS and DRRTC register sections are
identical to the write pointer delay formulas. To find the WPTRTC portion of write
pointer delay, use the DQSOFCS formulas, and substitute WPTRTC fields for all the
DQSOFCS fields. The only difference in the application of these formulas is that there is
only one WPTRTC field per byte of the DDR I/O, whereas the DQSOFCS has a field per
nibble per rank. The total write pointer delay, measured from the same reference point
as the DQS receiver enable timing, is equal to the DQS receiver enable timing,
including the quarter clock and sub-quarter clock delays, plus one full clock cycle, plus
the coarse and fine DRAMDLLC.SLVLEN/WPTRTC delays calculated with the formulas
from the DQSOFCS register section.
14.6.1.22 WPTRTC0: Write Pointer Timing Control 0
This register determines the DDR I/O FIFO write pointer fine delay timing for all DQS
signals except DQS17 and DQS8 when reading from rank 0 or rank 1.
Device:
NodeID
Function: 4
Offset:
Bit
CCh
Attr
Default
Description
31:28
27:24
23:20
19:16
15:12
11:8
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
0h
0h
0h
0h
0h
0h
0h
0h
DQS1607: DQS16 and DQS7 write pointer fine delay
DQS1506: DQS15 and DQS6 write pointer fine delay
DQS1405: DQS14 and DQS5 write pointer fine delay
DQS1304: DQS13 and DQS4 write pointer fine delay
DQS1203: DQS12 and DQS3 write pointer fine delay
DQS1102: DQS11 and DQS2 write pointer fine delay
DQS1001: DQS10 and DQS1 write pointer fine delay
DQS0900: DQS9 and DQS0 write pointer fine delay
7:4
3:0
Intel® 6400/6402 Advanced Memory Buffer Datasheet
217
INTEL [ INTEL ]
