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5M80ZE64I5N 参数 Datasheet PDF下载

5M80ZE64I5N图片预览
型号: 5M80ZE64I5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, 64-Cell, CMOS, PQFP64, 9 X 9 MM, 0.40 MM PITCH, LEAD FREE, PLASTIC, EQFP-64]
分类和应用:
文件页数/大小: 166 页 / 4004 K
品牌: INTEL [ INTEL ]
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Chapter 7: User Flash Memory in MAX V Devices  
7–31  
Software Support for UFM Block  
WREN (Write Enable)  
The interface is powered-up in the write disable state. Therefore, WENin the status  
register (refer to Table 7–11) is at power-up. Before any write is allowed to take  
place, WRENmust be issued to set WENin the status register to . If the interface is in  
0
1
read-only mode, WRENdoes not have any effect on WEN, because the status register does  
not exist. After WENis set to 1, it can be reset by the WRDIinstruction; the WRITEand  
SECTOR-ERASEinstructions will not reset the WENbit. WRENis issued through the  
following sequence, as shown in Figure 7–28:  
1. nCSis pulled low.  
2. Opcode 00000110is transmitted into the interface to set WENto  
1in the status  
register.  
3. After the transmission of the eighth bit of WREN, the interface is in wait state  
(waiting for nCSto be pulled back to high). Any transmission after this is ignored.  
4. nCSis pulled back to high.  
Figure 7–28. WREN Operation Sequence  
nCS  
0
1
2
3
4
5 6 7  
SCK  
SI  
8-bit  
Instruction  
06H  
MSB  
High Impedance  
SO  
January 2011 Altera Corporation  
MAX V Device Handbook  
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